Load Full Pointer (lds,les, lfs, lgs, and lss)
lds{wl} mem[32|48], reg[16|32]
les{wl} mem[32|48], reg[16|32]
lfs{wl} mem[32|48], reg[16|32]
lgs{wl} mem[32|48], reg[16|32]
lss{wl} mem[32|48], reg[16|32]
Operation
mem[32|48] -> reg[16|32]
Description
Reads a full pointer from memory and stores it in the specified segment register (DS,
ES, FS, GS or SS) with a 16- or 32-bit offset value.
insl ------- DX标明端口－＞ES：destination
outl (%dx) ------- EAX -> (%dx)标明的端口
outsl ------- ES:source -> DX标明的端口
lahf --- load flags into AH register
8位flag依次是：sign, zero, indeterminate, auxiliary carry, indeterminate, parity, indeterminate, and carry.
sahf --- store AH into flags
从AH中load flags的值
popf{wl} ----- pop stack into flag
popfw ----- pop the world from stack into flags register.
popfl ----- pop the long from stack into eflags register.
pushf{wl} ------- push flags register into stack.
cmc ---- complement carry flag, 反转carry flag的值 ( not CF -> CF)
clc ----- clear carry flag, 0 -> CF.
stc ---- set carry flag, 1 -> CF.
cli ---- clear interrupt flag, 关中断。（0 -> IF)
sti ------ set interrupt flag, 开中断。 （1 -> IF）
cld ------ clear direction flag, Causes all subsequent string operations to increment the index registers, (E)SI and/or (E)DI, used during
the operation. (0 -> DF)
std ------ set direction flag, causing all subsequent string operations to decrement the index registers, (E)SI and/or (E)DI,
used during the operation. (1 -> DF)
Integer Addition (add)
add{bwl} reg[8|16|32], r/m[8|16|32]
add{bwl} r/m[8|16|32], reg[8|16|32]
add{bwl} imm[8|16|32], r/m[8|16|32]
Operation
reg[8|16|32] + r/m[8|16|32] -> r/m[8|16|32]
r/m[8|16|32] + reg[8|16|32] -> reg[8|16|32]
imm[8|16|32] + r/m[8|16|32] -> r/m[8|16|32]
Description
Integer adds operand1 to operand2 and stores the result in operand2.
When an immediate byte is added to a word or long, the immediate value is
sign-extended to the size of the word or long operand.
If you wish to decimal adjust (daa) or ASCII adjust (aaa) the add result, use the
form of add that stores the result in AL.
Integer Add With Carry (adc)
adc{bwl} reg[8|16|32], r/m[8|16|32]
adc{bwl} r/m[8|16|32], reg[8|16|32]
adc{bwl} imm[8|16|32], r/m[8|16|32]
Operation:
(reg[8|16|32] + CF) + r/m[8|16|32] -> r/m[8|16|32]
(r/m[8|16|32] + CF) + reg[8|16|32] -> reg[8|16|32]
(imm[8|16|32] + CF) + r/m[8|16|32] -> r/m[8|16|32]
Description
Integer adds operand1 and the carry flag to operand2 and stores the result in
operand2. adc is typically executed as part of a multi-byte or multi-word add
operation. When an immediate byte is added to a word or long, the immediate value
is sign-extended to the size of the word or long operand.
Integer Subtraction (sub)
sub{bwl} reg[8|16|32], r/m[8|16|32]
sub{bwl} r/m[8|16|32], reg[8|16|32]
sub{bwl} imm[8|16|32], r/m[8|16|32]
Operation
r/m[8|16|32] - reg[8|16|32] -> r/m[8|16|32]
reg[8|16|32] - r/m[8|16|32] -> reg[8|16|32]
r/m[8|16|32] - imm[8|16|32] -> r/m[8|16|32]
Description
Subtracts operand1 from operand2 and stores the result in operand2. When an
immediate byte value is subtracted from a word, the immediate value is
sign-extended to the size of the word operand before the subtract operation is
executed.
If you wish to decimal adjust (das) or ASCII adjust (aas) the sub result, use the
form of sub that stores the result in AL.
Integer Subtraction With Borrow (sbb)
sbb{bwl} reg[8|16|32], r/m[8|16|32]
sbb{bwl} r/m[8|16|32], reg[8|16|32]
sbb{bwl} imm[8|16|32], r/m[8|16|32]
Operation
r/m[8|16|32] - (reg[8|16|32] + CF) -> r/m[8|16|32]
reg[8|16|32] - (r/m[8|16|32] + CF) -> reg[8|16|32]
r/m[8|16|32] - (imm[8|16|32] + CF) -> r/m[8|16|32]
Description
Subtracts (operand1 and the carry flag) from operand2 and stores the result in
operand2. When an immediate byte value is subtracted from a word, the immediate
value is sign-extended to the size of the word operand before the subtract operation
is executed.
Compare Two Operands (cmp)
cmp{bwl} reg[8|16|32], r/m[8|16|32]
cmp{bwl} r/m[8|16|32], reg[8|16|32]
cmp{bwl} imm[8|16|32], r/m[8|16|32]
Operation
r/m[8|16|32] - reg[8|16|32]
reg[8|16|32] - r/m[8|16|32]
r/m[8|16|32] - imm[8|16|32]
Description
Subtracts operand1 from operand2, but does not store the result; only changes the
flags. cmp is typically executed in conjunction with conditional jumps and the setcc
instruction. If an operand greater than one byte is compared to an immediate byte,
the immediate byte value is first sign-extended.
inc{bwl} r/m[8|16|32]
Operation
r/m[8|16|32] + 1 -> r/m[8|16|32]
Description
Adds 1 to the operand and does not change the carry flag. Use the add instruction
with an immediate value of 1 to change the carry flag,.
Decrease by 1 (dec)
dec{bwl} r/m[8|16|32]
Operation
r/m[8|16|32] - 1 -> r/m[8|16|32]
Description
Subtracts 1 from the operand. Does not change the carry flag. To change the carry
flag, use the sub instruction with an immediate value of 1.
Logical Comparison or Test (test)
test{bwl} reg[8|16|32], r/m[8|16|32]
test{bwl} r/m[8|16|32], reg[8|16|32]
test{bwl} imm[8|16|32], r/m[8|16|32]
Operation
reg[8|16|32] and r/m[8|16|32] -> r/m[8|16|32]
r/m[8|16|32] and reg[8|16|32] -> reg[8|16|32]
imm[8|16|32] and r/m[8|16|32] -> r/m[8|16|32]
Description
Performs a bit-wise logical AND of the two operands. The result of a bit-wise logical
AND is 1 if the value of that bit in both operands is 1; otherwise, the result is 0.
test discards the results and modifies the flags. The OF and CF flags are cleared; SF,
ZF and PF flags are set according to the result.
Shift (sal, shl, sar, shr)
shl{bwl} %cl, r/m[8|16|32] sar{bwl} imm8, r/m[8|16|32] sar{bwl} %cl, r/
m[8|16|32] shr{bwl} imm8, r/m[8|16|32]
sal{bwl} %cl, r/m[8|16|32]
shl{bwl} imm8, r/m[8|16|32]
sar{bwl} imm8, r/m[8|16|32]
shr{bwl} %cl, r/m[8|16|32]
Operation
shift-left r/m[8|16|32] by imm8 -> r/m[8|16|32]
shift-left r/m[8|16|32] by %cl -> r/m[8|16|32]
shift-right r/m[8|16|32] by imm8 -> r/m[8|16|32]
shift-right r/m[8|16|32] by %cl -> r/m[8|16|32]
Description
sal (or its synonym shl) left shifts (multiplies) a byte, word, or long value for a
count specified by an immediate value and stores the product in that byte, word, or
long respectively. The second variation left shifts by a count value specified in the CL
register. The high-order bit is shifted into the carry flag; the low-order bit is set to 0.
sar right shifts (signed divides) a byte, word, or long value for a count specified by
an immediate value and stores the quotient in that byte, word, or long respectively.
The second variation right shifts by a count value specified in the CL register. sar
rounds toward negative infinity; the high-order bit remains unchanged.
shr right shifts (unsigned divides) a byte, word, or long value for a count specified
by an immediate value and stores the quotient in that byte, word, or long
respectively. The second variation divides by a count value specified in the CL
register. shr sets the high-order bit to 0.
Double Precision Shift Left (shld)
shld{wl} imm8, reg[16|32], r/m[16|32]
shld{wl} %cl, reg[16|32], r/m[16|32]
Operation
by imm8 shift-left r/m[16|32] bits reg[16|32] -> r/m[16|32]
by reg[16|32] shift-left r/m[16|32] bits r/m[16|32] -> r/m[16|32]
Description
shld double-precision left shifts a 16- or 32-bit register value into a word or long for
the count specified by an immediate value, MODULO 32 (0 to 31). The result is
stored in that particular word or long.
The second variation of shld double-precision left shifts a 16- or 32-bit register or
memory value into a word or long for the count specified by register CL MODULO
32 (0 to 31).The result is stored in that particular word or long.
shld sets the SF, ZF, and PF flags according to the value of the result; CS is set to the
value of the last bit shifted out; OF and AF are undefined.
Double Precision Shift Right (shrd)
shrd{wl} imm8, reg[16|32], r/m[16|32]
shrd{wl} %cl, reg[16|32], r/m[16|32]
Operation
by imm8 shift-right r/m[16|32] bits reg[16|32] -> r/m[16|32]
by reg[16|32] shift-right r/m[16|32] bits r/m[16|32] -> r/m[16|32]
Description
shrd double-precision right shifts a 16- or 32-bit register value into a word or long
for the count specified by an immediate value MODULO 32 (0 to 31). The result is
stored in that particular word or long.
The second variation of shrd double-precision right shifts a 16- or 32-bit register or
memory value into a word or long for the count specified by register CL MODULO
32 (0 to 31).The result is stored in that particular word or long.
shrd sets the SF, ZF, and PF flags according to the value of the result; CS is set to the
value of the last bit shifted out; OF and AF are undefined.
将目的操作数(r/m[16|32])向右移动相应位数(imm8)，空出来的位由源操作数(reg[16|32])的低位填充。
例：
movw 1234h, ax
movw 5678h, bx
shrdw 16, bx, ax ;ax=5678h
movl 12345678h, eax
movl 87654321h, ebx
shrdl 32, ebx, eax ;eax=12345678h，右移8字节，eax不变，
shrdl 28, ebx, eax ;eax=76543211h，右移7字节还是可以的。
因为shrd的移位数是做了mod 32限制的，移32位就是移0位, 而移16位是没有问题的。
One’s Complement Negation (not)
not{bwl} r/m[8|16|32]
Operation
not r/m[8|16|32] -> r/m[8|16|32]
Description
Inverts each bit value of the byte, word, or long; that is, every 1 becomes a 0 and
every 0 becomes a 1.
Two’s Complement(补码） Negation (neg)
neg{bwl} r/m[8|16|32]
Operation
two’s-complement r/m[8|16|32] -> r/m[8|16|32]
Description
Replace the value of the byte, word, or long with its two’s complement; that is, neg
subtracts the byte, word, or long value from 0, and puts the result in the byte, word,
or long respectively.
neg sets the carry flag to 1, unless initial value of the byte, word, or long is 0. In this
case neg clears the carry flag to 0.
neg指令将src中的内容取2的补码后，再送回src中。因取2补码相当于(src)ß 0－(src)，所以NEG指令执行的操作也是减法操作。
0-(src)又相当于：0FFH－(src)＋1(字节操作数)或0FFFFH-(src)＋1(字操作数)，即将src内容变反加1。
例如：若(AL)=13H，执行NEG AL指令后，(AL)=0EDH；若(AL)＝0AFH执行NEG AL后，(AL)=51H。
因为在计算机的记数法中，记数的位数是有限制的，比如8位二进制位最大只能表示FFH，十六位二进制位最大只能表示FFFFH，而FFH+1=00H或 FFFFH+1=0000H，
这时会发生进位，体现在CF中，标志位CF=1。
Check Array Index Against Bounds (bound)
bound{wl} reg[16|32], r/m[16|32]
Operation
r/m[16|32] bound reg[16|32] -> CC is unchanged
Description
Ensures that a signed array index (16- or 32-bit register) value falls within the upper
and lower bounds of a block of memory. The upper and lower bounds are specified
by a 16- or 32-bit register or memory value. If the signed array index value is not
within the bounds, an Interrupt 5 occurs; the return EIP points to the bound
instruction.
16位/32位寄存器的内容与寻址到的存储器中的两个字/双字进行比较，两个字/双字作为比较的上限和下限。若比较后，寄存器的内容不在上下界限内，
则产生5号中断；若在上下界限内，则继续执行程序中下一条指令。
Logical And (and)
and{bwl} reg[8|16|32], r/m[8|16|32]
and{bwl} r/m[8|16|32], reg[8|16|32]
and{bwl} imm[8|16|32], r/m[8|16|32]
Operation
reg[8|16|32] land r/m[8|16|32] －＞ r/m[8|16|32]
r/m[8|16|32] land reg[8|16|32] －＞ reg[8|16|32]
imm[8|16|32] land r/m[8|16|32] －＞ r/m[8|16|32]
Description
Performs a logical AND of each bit in the values specified by the two operands and
stores the result in the second operand.
Logical Inclusive OR (or)
or{bwl} reg[8|16|32], r/m[8|16|32]
or{bwl} r/m[8|16|32], reg[8|16|32]
or{bwl} imm[8|16|32], r/m[8|16|32]
Operation
reg[8|16|32] LOR r/m[8|16|32] －＞ r/m[8|16|32]
r/m[8|16|32] LOR reg[8|16|32] －＞ reg[8|16|32]
imm[8|16|32] LOR r/m[8|16|32] －＞ r/m[8|16|32]
Description
Performs a logical OR of each bit in the values specified by the two operands and
stores the result in the second operand.
Logical Exclusive OR (xor)
xor{bwl} reg[8|16|32], r/m[8|16|32]
xor{bwl} r/m[8|16|32], reg[8|16|32]
xor{bwl} imm[8|16|32], r/m[8|16|32]
Operation
reg[8|16|32] XOR r/m[8|16|32] －＞ r/m[8|16|32]
r/m[8|16|32] XOR reg[8|16|32] －＞ reg[8|16|32]
imm[8|16|32] XOR r/m[8|16|32] －＞ r/m[8|16|32]
Description
Performs an exclusive OR of each bit in the values specified by the two operands
and stores the result in the second operand.
Signed Multiply (imul)
imulb r/m8
imulw r/m16
imul{l} r/m32
imul{wl} r/m[16|32], reg[16|32]
imul{bwl} imm[16|32], r/m[16|32], reg[16|32]
Operation
r/m8 * AL -> AX
r/m16 * AX -> DX:AX
r/m32 * EAX -> EDX:EAX
r/m[16|32] * reg[16|32] -> reg|16|32]
imm[16|32] * r/m[16|32] -> reg|16|32]
Description
The single-operand form of imul executes a signed multiply of a byte, word, or long
by the contents of the AL, AX, or EAX register and stores the product in the AX,
DX:AX or EDX:EAX register respectively.
The two-operand form of imul executes a signed multiply of a register or memory
word or long by a register word or long and stores the product in that register word
or long.
The three-operand form of imul executes a signed multiply of a 16- or 32-bit
immediate by a register or memory word or long and stores the product in a
specified register word or long.
imul clears the overflow and carry flags under the following conditions:
Unsigned Multiplication of AL, AX or EAX(mul)
mul{bwl} r/m[8|16|32]
Operation
r/m8 * AL -> AX
r/m16 * AX -> DX:AX
r/m32 * EAX -> EDX:EAX
Description
mul executes a unsigned multiply of a byte, word, or long by the contents of the AL,
AX, or EAX register and stores the product in the AX, DX:AX or EDX:EAX register
respectively.
mul clears the overflow and carry flags under the following conditions:
Unsigned Divide (div)
div{bwl} r/m[8|16|32]
Operation
AX r/m8 -> AL DX:AX
r/m16 ! AX EDX:EAX
r/m32 ! EAX
Description
div executes unsigned division. div divides a 16-, 32-, or 64-bit register value
(dividend) by a register or memory byte, word, or long (divisor). The quotient is
stored in the AL, AX, or EAX register respectively.
The remainder is stored in AH, Dx, or EDX. The size of the divisor (8-, 16- or 32-bit
operand) determines the particular register used as the dividend.
The OF, SF, ZF, AR, PF and CF flags are undefined.
Example
Perform an 8-bit unsigned divide of the AX register by the contents of the effective
address (addressed by the ESI register plus an offset of 1) and store the quotient in
the AL register, and the remainder in AH:
divb 1(%esi)
Signed Divide (idiv)
idiv{bwl} r/m[8|16|32]
Operation
AX r/m8 -> AL
DX:AX r/m16 -> AX
EDX:EAX r/m32 -> EAX
Description
idiv executes signed division. idiv divides a 16-, 32-, or 64-bit register value
(dividend) by a register or memory byte, word, or long (divisor). The size of the
divisor (8-, 16- or 32-bit operand) determines the particular register used as the
dividend, quotient, and remainder.
Conversion Instructions
Convert Byte to Word (cbtw)
cbtw
Operation
sign-extend AL -> AX
Description
cbtw converts the signed byte in AL to a signed word in AX by extending the
most-significant bit (sign bit) of AL into all bits of AH.
Convert Word to Long (cwtl)
cwtl
Operation
sign-extend AX -> EAX
Description
cwtl converts the signed word in AX to a signed long in EAX by extending the
most-significant bit (sign bit) of AX into two most-significant bytes of EAX.
Convert Signed Word to Signed Double Word
(cwtd)
cwtd
Operation
sign-extend AX -> DX:AX
Description
cwtd converts the signed word in AX to a signed double word in DX:AX by
extending the most-significant bit (sign bit) of AX into all bits of DX.
Convert Signed Long to Signed Double Long (cltd)
cltd
Operation
sign-extend EAX -> EDX:EAX
Description
cltd converts the signed long in EAX to a signed double long in EDX:EAX by
extending the most-significant bit (sign bit) of EAX into all bits of EDX.
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