OPERATING MODES

OPERATING MODES
ARM7TDMI supports seven modes of operation:
??User (usr): The normal ARM program execution state
??FIQ (fiq): Designed to support a data transfer or channel process
??IRQ (irq): Used for general-purpose interrupt handling
??Supervisor (svc): Protected mode for the operating system
??Abort mode (abt): Entered after a data or instruction prefetch abort
??System (sys): A privileged user mode for the operating system
??Undefined (und): Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Most application programs will execute in User mode. The non-user modes' known as privileged
modes-are entered in order to service interrupts or exceptions, or to access protected resources.
REGISTERS
ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these
cannot all be seen at once. The processor state and operating mode dictate which registers are available to the
programmer.
The ARM State Register Set
In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non-
User) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in
each mode: the banked registers are marked with a shaded triangle.
The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are
general-purpose, and may be used to hold either data or address values. In addition to these, there is a
seventeenth register used to store status information.
Register 14 is used as the subroutine link register. This receives a copy of R15 when a Branch
and Link (BL) instruction is executed. At all other times it may be treated as a
general-purpose register. The corresponding banked registers R14_svc, R14_irq,
R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15
when interrupts and exceptions arise, or when Branch and Link instructions are
executed within interrupt or exception routines.
Register 15 holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits
[31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.
Register 16 is the CPSR (Current Program Status Register). This contains condition code flags
and the current mode bits.
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do
not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers
mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.

作模式

ARM7TDMI的支持7种工作模式：

??用户（usr）：ARM公司的正常程序执行状态

??智商（智商）：为支持的数据传输或通道处理

??的IRQ（IRQ）的：一般用途使用的中断处理

??主管（简称SVC）：受保护的操作系统的模式

??中止模式（ABT生根粉）：输入后，数据或指令预取中止

??系统（一高）：一种操作系统的特权用户模式

??未定义（达科）：当输入一个未定义指令执行

模式的改变，可根据软件控制，或可能对外部中断或异常带

加工。大多数的应用程序将在用户模式下执行。非用户模式'的特权称为

模式，是为了进入服务中断或异常，或访问受保护的资源。

登记册

ARM7TDMI的有37册- 31个通用32位寄存器和状态寄存器6 -但总这些

不能看到所有的一次。该处理器状态和运行模式主宰的寄存器可用

程序员。

此外，ARM状态寄存器集