7、Clock Power时钟--s3c2440

一、s3c2440 时钟

    The Clock control logic in S3C2440A can generate the required clock signals including FCLK for CPU,

 HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals. The S3C2440A has two Phase

 Locked Loops (PLLs):one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz).

 The clock control logic can make slow clocks without PLL and connect/disconnect the clock to each 

peripheral block by software, which will reduce the power consumption.

二、寄存器

MPLLCON 0x4C000004 R/W MPLL configuration register 0x00096030

UPLLCON 0x4C000008 R/W UPLL configuration register 0x0004d030

CLKDIVN 0x4C000014 R/W Clock divider control register 0x00000000

#define MDIV_400_148 0x5c

#define PDIV_400_148 0x1

#define SDIV_400_148 0x1

#define CLKDVIN_400_148 0x5   /* 1:4:8 */

Fin=12MHZ

Mpll = (2 * m * Fin) / (p * 2^s)=400M

m = (MDIV + 8), p = (PDIV + 2), s = SDIV

m=0x5c+8=100

p=1+2=3

s=1

FCLK:HCLK:PCLK = 1:4:8，因此得出HCLK=100Mhz

Mpll = (2*m * Fin) / (p * 2s)

m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2

三、源程序

start.S

/*
 *************************************************************************
 *
 * lcl bootloader
 *
 *************************************************************************
 */

.globl _start
_start:    b    start_code


start_code:
    /*
     * set the cpu to SVC32 mode
     */
    mrs    r0, cpsr
    bic    r0, r0, #0x1f
    orr    r0, r0, #0xd3
    msr    cpsr, r0

    bl clock_init
    bl cpu_init_crit
    bl copy_code_to_sdram

    /*
     *run in sdram
     */

    ldr sp, =0x34000000
    ldr lr, =halt_loop          @璁剧疆杩斿洖鍦板潃
    ldr pc, =    Main                     //0x30100034


halt_loop:
   b halt_loop

   /*
    * copy code from interal 4K sdram to sdram
    */

copy_code_to_sdram:

#define SDRAM_BASE 0x30000000

    mov r1,#2048
    ldr r2,=0x30100000
    mov r3,#4*1024

1:
    ldr r4,[r1],#4
    str r4,[r2],#4
    cmp r1,r3
    bne 1b
    mov pc,lr

    /*
     *clock initialize. Mpll=405MHZ 1:4:8
     */
clock_init:

#define pWTCON            0x53000000
#define INTMSK            0x4A000008     /* Interupt-Controller base addresses */
#define INTSUBMSK        0x4A00001C
#define CLKDIVN            0x4C000014     /* clock divisor register */
#define CLK_CTL_BASE    0x4C000000    /* clock base address */

#define MDIV_405        0x7f << 12    /* MDIV 0x7f*/
#define PSDIV_405        0x21        /* PDIV SDIV 0x2 0x1 */

        /* turn off the watchdog */

        ldr r0, =pWTCON
        mov r1, #0x0
        str r1, [r0]

        /*
         * mask all IRQs by setting all bits in the INTMR - default
         */

        ldr r1, =0x7fff
        ldr r0, =INTSUBMSK
        str r1, [r0]

        /* FCLK:HCLK:PCLK = 1:4:8 */
        ldr r0, =CLKDIVN
        mov r1, #5                 //1:4:8

        str r1, [r0]

        mrc p15, 0, r1, c1, c0, 0    //切换到实时总线HCLK

        orr r1, r1, #0xc0000000
        mcr p15, 0, r1, c1, c0, 0


        mov r1, #CLK_CTL_BASE
        mov r2, #MDIV_405
        add r2, r2, #PSDIV_405
        str r2, [r1, #0x04]     /* MPLLCON address     Mpll=405MHZ */


    /*
     *MMU and SDRAM initialize
     */

cpu_init_crit:
    /*
     * flush v4 I/D caches
     */
    mov    r0, #0
    mcr    p15, 0, r0, c7, c7, 0    /* flush v3/v4 cache */
    mcr    p15, 0, r0, c8, c7, 0    /* flush v4 TLB */

    /*
     * disable MMU stuff and caches
     */
    mrc    p15, 0, r0, c1, c0, 0
    bic    r0, r0, #0x00002300    @ clear bits 13, 9:8 (--V- --RS)
    bic    r0, r0, #0x00000087    @ clear bits 7, 2:0 (B--- -CAM)
    orr    r0, r0, #0x00000002    @ set bit 2 (A) Align
    orr    r0, r0, #0x00001000    @ set bit 12 (I) I-Cache
    mcr    p15, 0, r0, c1, c0, 0

    /*
     * before relocating, we have to setup RAM timing
     * because memory timing is board-dependend, you will
     * find a lowlevel_init.S in your board directory.
     */
    mov    ip, lr

    bl memsetup     /* memory control configuration */

    mov    lr, ip
    mov    pc, lr

memsetup:
    /* memory control configuration */
    /* make r0 relative the current location so that it */
    /* reads SMRDATA out of FLASH rather than memory ! */

#define MEM_CTL_BASE    0x48000000

    mov r1,#MEM_CTL_BASE
    adr r2,mem_cfg_val
    add r3,r1,#52
1:
    ldr     r4, [r2], #4
    str     r4, [r1], #4
    cmp     r1, r3
    bne     1b
    mov     pc,lr

.align 4
        /* the literal pools origin */
mem_cfg_val:
    .long        0x22011110
    .long        0x00000700
    .long        0x00000700
    .long        0x00000700
    .long        0x00000700
    .long        0x00000700
    .long        0x00000700    @BANK5
    .long        0x00018005
    .long        0x00018005
    .long        0x00ac03f4    @REFRESH // 12MHZ 0x00ac07a3

    .long        0x000000B1
    .long        0x00000030
    .long        0x00000030

main.c

 

/*
GPBCON 0x56000010 Port B control
GPBDAT 0x56000014 Port B data
GPBUP 0x56000018 Pull-up control B

LED1 GPB5 LED2 GPB6 LED3 GPB7 LED4 GPB8

GPB8 [17:16] 00 = Input 01 = Output
             10 = nXDREQ1 11 = Reserved
GPB7 [15:14] 00 = Input 01 = Output
             10 = nXDACK1 11 = Reserved
GPB6 [13:12] 00 = Input 01 = Output
             10 = nXBREQ 11 = reserved
GPB5 [11:10] 00 = Input 01 = Output
             10 = nXBACK 11 = reserved
#define S3C24X0_GPIO_BASE        0x56000000

GPGCON = 0000 0000 1000 0000 1010 1000 1000 0010=0x80a882

GPG0 Input/output EinT8 – – K1
GPG3 Input/output EinT11 nSS1 –     K2
GPG5 Input/output EinT13 SPIMISO1 – k3
GPG6 Input/output EinT14 SPIMISO1 – k4
GPG7 Input/output EinT15 SPICLK1 – k5
GPG11 Input/output EinT19 TCLK1 – k6
*/

#define GPBCON (*(volatile unsigned long *) 0x56000010)
#define GPBDAT (*(volatile unsigned long *) 0x56000014)
#define GPBUP (*(volatile unsigned long *) 0x56000018)

#define GPGCON (*(volatile unsigned long *) 0x56000060)
#define GPGDAT (*(volatile unsigned long *) 0x56000064)
#define GPGUP (*(volatile unsigned long *) 0x56000068)

#define GPX_up 0x00000000

#define GPB5_out (1<<(5*2))
#define GPB6_out (1<<(6*2))
#define GPB7_out (1<<(7*2))
#define GPB8_out (1<<(8*2))

#define GPG0_in ~(3<<(0*2))
#define GPG3_in ~(3<<(3*2))
#define GPG5_in ~(3<<(5*2))
#define GPG6_in ~(3<<(6*2))

void leds_init()
{
    GPBCON = (GPB5_out | GPB6_out | GPB7_out | GPB8_out);
    GPBUP     = GPX_up;
}
void buttons_init()
{
    GPGCON = (GPG0_in & GPG3_in & GPG5_in & GPG6_in);
    GPGUP     = GPX_up;
}

int Main()
{
    unsigned long dwDat;
    leds_init();
    buttons_init();

    while (1)
    {
        dwDat=GPGDAT;
        if(dwDat & (1<<0))
            GPBDAT |=(1<<5);
        else
            GPBDAT &=~(1<<5);

        if(dwDat & (1<<3))
            GPBDAT |=(1<<6);
        else
            GPBDAT &=~(1<<6);

        if(dwDat & (1<<5))
            GPBDAT |=(1<<7);
        else
            GPBDAT &=~(1<<7);

        if(dwDat & (1<<6))
            GPBDAT |=(1<<8);
        else
            GPBDAT &=~(1<<8);
    }

    return 0;
}

mem.lds

SECTIONS {
  firtst     0x00000000 : { start.o}
  second     0x30000800 : AT(2048) { main.o }
}

makefile

 

objs := start.o main.o

sdram.bin : $(objs)
    arm-linux-ld -Tsdram.lds    -o sdram_elf $^
    arm-linux-objcopy -O binary -S sdram_elf $@
    arm-linux-objdump -D -m arm sdram_elf > sdram.dis

%.o:%.c
    arm-linux-gcc -Wall -c -O2 -o $@ $<

%.o:%.S
    arm-linux-gcc -Wall -c -O2 -o $@ $<

clean:
    rm -f sdram.dis sdram.bin sdram_elf *.o

以下为能直接运行的二进制文件，下载到Nand Flash 的 Black0 直接以Nand Flash运行.

 sdram.rar