单电源运算放大器的偏置与往耦电路设计

目前在很多手持设备、汽车以及计算机等设备只用单电源供电，但是单电源轻易出现不稳定题目，因此需要在电路外围增加辅助器件以进步稳定性。在电路图1中展示了单电源供电运算放大器的偏置方法，用电阻RA与电阻RB构成分压电路，并把正输进真个电压设置为Vs/2。输进信号VIN是通过电容耦合到正输进端。在该电路中有一些严重的局限性。

首先，电路的电源抑制几乎没有，电源电压的任何变化都将直接通过两个分压电阻改变偏置电压Vs/2，但电源抑制的能力是电路非常重要的特性。例如此电路的电源电压1伏的变化，能引起偏置电路电压的输出Vs/2变化0.5伏。该电路的电源抑制仅仅只有6dB，通过选用SGM8541运算放大器可以增强电源抑制能力。

图1：单电源供电运算放大器的偏置方法。

图1：单电源供电运算放大器的偏置方法。

其次，运算放大器驱动大电流负载时电源经常不稳定，除非电源有很好的调节能力，或有很好的旁路，否则大的电压波动将回馈到电源线路上。运算放大器的正输进真个参考点将直接偏离Vs/2，这些信号将直接流进放大器的正输进端。

表1：适用于图2的典型器件值。

在应用中要特别留意布局，多个电源旁路电容、星形接地、单独的印制电源层可以提供比较稳定的电路。

偏置电路的往耦题目

解答这个题目需要改变一下电路。图2从偏置电路的中间节点接电容C2，用来旁路AC信号，这样可以进步AC的电源抑制，电阻RIN为Vs/2的基准电压提供DC的返回通路，并且为AC输进提供了交流输进阻抗。

图2：接电容C2来旁路AC信号，进步AC的电源

ust generate the early-warning and reset signals while monitoring the same regulated supply. You can use a single threshold detector for the low-line signal plus a delay timer for the reset signal, or use two different comparators—one for tLOWLINE and one for tRST. Either way, you must ensure that VCC remains valid long enough to complete the shutdown routine that follows an interrupt from the low-line signal.

The time required to complete a shutdown/backup routine varies widely with the application, as does the fall rate of VCC. Thus, you must adjust the delay from low-line to reset according to the application. The two-threshold approach is more flexible than the time-delayed-reset approach. By adjusting the low-line threshold tens of millivolts above the reset threshold and adjusting the VCC fall rate to comply with time requirements for the shutdown routine, you can make one IC serve many different applications.

In most battery-operated portable systems, reserve energy in the battery provides ample time to complete the shutdown routine during the interval between the low-line warning and reset. If the VCC fall time is rapid, as when a high-side switch is opened during normal operation, add capacitance on the load side of the switch to slow the decline of VCC and provide time for executing the shutdown routine. In MAX814 supervisors, for example, the power-fail comparator's delay (less than 50s) may or may not affect your application.

First, calculate the worst-case time required for the shutdown routine. Using this value, the worst-case load current, and the minimum low-line to reset-threshold difference (VLR(min)), calculate the capacitance necessary for completion of the shutdown routine before reset occurs:




where ILOAD is the current being drained from the capacitor, VLR(min) is the minimum difference between the low-line and reset thresholds, and tSHDN is the time required for an orderly shutdown to occur, including the reset comparator's propagation delay.

Placing the low-line threshold above the reset threshold can allow false low-line triggers due to noise. To overcome this problem, filter the noise with adequate bypassing, and use software to monitor the low-line interrupt after the shutdown routine is completed. When the processor receives an interrupt from the low-line comparator, it completes the backup/shutdown routine and then returns to monitor the interrupt. If a line or load transient causes low-line to return high relatively quickly, the software initiates a "warm" start-up by reloading the stored parameters. If a power failure occurs, the low-line signal is followed by a reset signal, and the normal battery-backup mode of operation begins.

DC-DC Boost Circuit Extends Shutdown Time

If a backup/shutdown routine requires more time than you can reasonably provide with storage capacitors, you can use a dc-dc converter to sustain VCC while the shutdown routine is in progress. The P can then shut down the dc-dc converter once the backup is complete.

In Figure 4, for example, IC2 is a step-up converter that provides 5V to the system and P supervisor (IC3) when the main 5V supply fails. At the onset of such a power failure, as the main supply falls below 4.65V, IC1 turns off Q1, brings IC2 out of shutdown, and interrupts the P. IC2 then boosts the supply voltage from 4.65V back to 5V. The reset threshold is not encountered, so a reset to the P is not issued. When the P finishes its shutdown routine, it simply pulls IC2 into shutdown again and the system goes into its normal battery-backup mode.


Figure 4. A threat of VCC loss causes the boost converter (IC3) to turn on and restore VCCto its nominal level.

The boost converter delivers up to 100mA while powered from a lithium cell that has been drained to 2.5V. If desired, you can provide separate batteries for the RAM backup and the boost converters.

Guarding Against False Resets

The supervisory circuit must not issue resets in response to system noise or VCC load transients. About 50mV of noise on the digital power-supply lines is common. Load transients, which occur when modules, peripherals, and other subsystems are turned on or off, can cause serious problems if the reset comparator's propagation delay is too short.

You can avoid false resets by choosing a supervisory circuit whose reset comparator has a propagation delay of 10s to 30s. Shorter propagation delays (of a few hundred nanoseconds) react quickly to VCC transients, and are therefore likely to generate false resets. Long delays, on the other hand, can allow VCC to fall too far outside the system IC's operating range before the processor is reset. The majority of 5V applications include sufficient capacitance to reduce the VCC fall rate such that a reset occurs before VCC falls below the minimum level specified in the IC's electrical characteristics.

Battery Backup

For critical systems that require non-volatile memory, the designer can choose either erasable/programmable memory or a CMOS RAM with backup battery. EEPROMs and flash memory are rated not only for memory capacity, but also for the number of write cycles they can undergo. The most common non-volatile memory includes a switch that connects the CMOS RAM to the lithium backup battery or VCC, whichever is higher.

Large capacitors (around 0.5F) offer a popular method for providing a short-duration memory backup. Called SuperCaps or MaxCaps, these capacitors charge from VCC through a diode during normal operation (Figure 5). Charging current is limited by the capacitors' internal series resistance, which is relatively high. The RAM is switched from VCC to the capacitor when VCC collapses below the IC's reset threshold. The available backup time depends on the level of quiescent current into the RAM and superv

uring the timeout, or if VCC dips below threshold during normal operation, Q1 turns off and removes VCC from the load. During power-down as well, Reset goes high and turns Q1 off as soon as VCC drops below the threshold. IC1 maintains this gate drive for VCC down to 1V; below that level, the load remains safe because VGS is too low to turn Q1 back on.

This circuit can be implemented with any microprocessor-reset device offering an active-high, push-pull reset output. As alternatives offering other threshold levels and feature combinations, consider the MAX812, MAX824, MAX6327, and MAX6332.

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