操作码，也就是助记符，说明指令需要执行的操作类型
Cond 指令执行条件码，在编码中占4bit，0b0000 - 0b1110
S 条件码设置项,决定本次指令执行是否影响PSTATE寄存器响应状态位值
Rd/Xt 目标寄存器，A32指令可以选择R0-R14,T32指令大部分只能选择RO-R7，A64指令可以选择X0-X30 or W0-W30
Rn/Xn 第一个操作数的寄存器，和Rd一样，不同指令有不同要求
Opcode2 第二个操作数，可以是立即数，寄存器Rm和寄存器移位方式（Rm，#shit）
A64条件码：
一般目的寄存器命名：
指令分类：
Branches, Exception generating, and System instructions
Loads and stores
Data processing - immediate
Data processing - register
Data processing - SIMD and floating-point
1. Branch
B.cond ;19-bit signed PC-relative branch offset variant
CBNZ < Wt|Xt >, < label > ;Compare and branch if nonzero to a label at a PC-relative offset, without affecting the condition flags, and with a hint that this is not a subroutine call or return
CBZ < Wt|Xt >, < label > ;Compare and branch if zero to a label at a PC-relative offset, without affecting the condition flags, and with a hint
that this is not a subroutine call or return
TBNZ < Wt|Xt >, #< imm >, < label > ;Test bit and branch if nonzero to a label at a PC-relative offset, without affecting the condition flags, and with a hint that this is not a subroutine call or return
TBZ < Wt|Xt >, #< imm >, < label > ;Test bit and branch if zero to a label at a PC-relative offset, without affecting the condition flags, and with a hint that this is not a subroutine call or return
B < label > ;Branch unconditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or return, 26-bit signed PC-relative branch offset variant,
BL < label >
;Branch with link, calls a subroutine at a PC-relative offset, setting register X30 to PC + 4
BLR < Xn >
;Branch with link to register, calls a subroutine at an address in a register, setting register X30 to PC + 4
BR < Xn >
;Branch to register, branches unconditionally to an address in a register, with a hint that this is not a subroutine return
RET {< Xn >}
;Return from subroutine, branches unconditionally to an address in a register, with a hint that this is a subroutine return
2. Exception generating
( Is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the imm16 field)
BRK #< imm >
;Self-hosted debug breakpoint
HLT #< imm > ;External debug breakpoint
HVC #< imm >
;Generate exception targeting exception level 2
SMC #< imm >
;Generate exception targeting exception level 3
SVC #< imm >
;Generate exception targeting exception level 1
ERET
;Exception return using current ELR and SPSR
DCPS1 {#< imm >}
;Debug switch to exception level 1
DCPS2 {#< imm >}
;Debug switch to exception level 2
DCPS3 {#< imm >}
;Debug switch to exception level 3
DRPS
;Debug restore processor state
3. System instructions
MRS < Xt >, < systemreg >
;Move from system register
MSR < systemreg >, < Xt >
;Move to system register
MSR < pstatefield >, #< imm >
;Move immediate to processor state field
SYS #< op1 >, < Cn >, < Cm >, #< op2 >{, < Xt >}
;System instruction
SYSL < Xt >, #< op1 >, < Cn >, < Cm >, #< op2 >
;System instruction with result
IC < ic_op >{, < Xt >}
;Instruction cache operation
DC < dc_op >, < Xt >
;Data cache operation
AT < at_op >, < Xt >
;Address translate
TLBI < tlbi_op >{, < Xt >}
;TLB invalidate operation
NOP
;No operation
YIELD
;Yield hint
WFE
;Wait for event
WFI
;Wait for interrupt
SEV
;Send event
SEVL
;Send event local
HINT #< imm >
;Hint instruction
CLREX {#< imm >}
;Clear exclusive monitor
DSB < option >|#< imm >
;Data synchronization barrier
DMB < option >|#< imm >
;Data memory barrier
ISB {< option >|#< imm >}
;Instruction synchronization barrier
4. Loads and stores
LDR < Wt|Xt >, [< Xn|SP >, < R >< m >{, < extend > {< amount >}}]
;Load register (register offset)
LDR < Wt >, [< Xn|SP >], #< simm > ;Load register (immediate offset)
LDR < Wt >, < label > ;Load register (PC-relative literal)
STR < Wt|Xt >, [< Xn|SP >, < R >< m >{, < extend > {< amount >}}] ;Store register (register offset)
STR < Wt|Xt >, [< Xn|SP >], #< simm > ;Store register (immediate offset)
LDUR < Wt|Xt >, [< Xn|SP >{, #< simm >}] ;Load register (unscaled offset)
STUR < Wt|Xt >, [< Xn|SP >{, #< simm >}] ;Store register (unscaled offset)
LDP < Wt1|Xt1 >, < Wt2|Xt2 >, [< Xn|SP >], #< imm > ;Load pair of registers
STP < Wt1|Xt1 >, < Wt2|Xt2 >, [< Xn|SP >], #< imm > ;Store pair of registers
LDNP < Wt1|Xt1 >, < Wt2|Xt2 >, [< Xn|SP >{, #< imm >}] ;Load pair of registers, with non-temporal hint
STNP < Wt1|Xt1 >, < Wt2|Xt2 >, [< Xn|SP >{, #< imm >}] ;Store pair of registers, with non-temporal hint
LDTR < Wt|Xt >, [< Xn|SP >{, #< simm >}] ;Load register (unprivileged)
STTR < Wt|Xt >, [< Xn|SP >{, #< simm >}] ;Store register (unprivileged)
LDXR < Wt|Xt >, [< Xn|SP >{, #0}] ;Load exclusive register
STXR < Ws|Xs >, < Wt|Xt >, [< Xn|SP >{, #0}] ;Store exclusive register, returning status
LDAR < Wt|Xt >, [< Xn|SP >{, #0}] ;Load-acquire register
STLR < Wt|Xt >, [< Xn|SP >{, #0}] ;Store-release register
LDAXR < Wt|Xt >, [< Xn|SP >{, #0}] ;Load-acquire exclusive register
STLXR < Ws|Xs >, < Wt|Xt >, [< Xn|SP >{, #0}] ;Store-release exclusive register, returning status
5. Data processing
