读书报告——张静

要点摘要：

 

实验模型

We configure our simulator to model heterogeneous multi-core processors with big and small cores. The big core is a 4-wide out-of-order processor core; the small core is a 4-wide (stall-on-use) in-order processor core2.我们用大小核心来构成我们的异构多核处理器。大核心是一个4线无序的处理核心；小核心是一个4线的有序核心。

We assume both cores run at a 2 GHz clock frequency. Further, we assume a cache hierarchy consisting of three levels of cache, separate 32 KB L1 instruction and data caches, a 256 KB L2 cache and a 4 MB last-level L3 cache (LLC).我们假设每个核心的运行频率为2GHZ，然后，我们假设缓存层次有三层，分别是：单独的32kb的指令和数据层L1，一个256KB的缓存数据层L2和一个人4Mb的缓存曾L3

我们假定L1和L2高速缓存层用来评估这篇报告里边所有的配置。

Finally,we assume an aggressive stream-based hardware prefetcher; we experimentally evaluated that hardware prefetching improves performance by 47% and on average for the small and big cores, respectively.

最后，我们假定一个基于流的硬件预取器；我们试验中估出硬件预取器平均将小核心的性能提高了47%，大核心的性能提高了25%。

 

 

Results and Analysis

结果与分析

We evaluate dynamic PIE scheduling on private and shared LLCs with LRU, and a shared LLC with RRIP replacement.

我们将PIE的进程单独评估并将LLCs与LRU分享，一个共有的LLC用RRIP代替。

We compare PIE scheduling to a sampling-based strategythat assumes running a workload for one time interval on one core and for the next time interval on the other core. The workload-core schedule that yields the highest performance is then maintained for the next 10 time intervals, after which the sampling phase is reinitiated.

我们将PIE调度策略与采样调度策略进行比较，讲一个进程以[2, 18, 19, 33]为间隔，分别在两个核心上运行并记录数据。PIE调度算法在达到最佳性能之后的十次间隔内将会保持最佳性能，而采样调度则会重复这个过程。

 

 

总结：这两节主要讲了验证PIE调度算法的优越性的实验以及实验结果的分析，实验证明PIE调度算法比以前被认为是最好的调度算法相比具有优越性，PIE调度算法达到最高性能之后会保持这个性能不变，而采样调度则会不停地重负先前的内容。

 

 

问题:实验过程看的不是很清楚，三个缓存区的功能及各自负责的工作看的不是很明晰。