#define CLKDIVN 0X4C000000
#define CLK_CTL_BASE 0x4c000000
#define MDIV_405 0x7f<<12
#define PSDIV_405 0x21
/*FCLK:HCLK:PCLK = 1:4:8*/
ldr r0, =CLKDIVN
mov r1, #5
str r1, [r0]
mrc p15, 0, r1, c1, c0, 0
orr r1, r1, #0xc0000000
mcr p15, 0, r1, c1, c0, 0
mov r1, #CLK_CTL_BASE
mov r2, #MDIV_405
add r2, r2, #PADIV_405
str r2, [r1, #0x4]
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