全部博文(48)
分类: LINUX
2013-01-28 10:59:56
Microarchitecture
1 Memory bus
2 System bus: HyperTransport
Instructions set MIPS LISA64
1 HyperTransport: 主频,FSB频率,外频。HT类似QPI,是FSB的drop-in。
2 双通道
3 Crossbar:X1物理空间自身映射,X2物理空间到PCI和内存的映射。
compiled method is in the homepage, ppt given by leader is a big KENG.
Compile environment:
Configure file:
1 Global conf file conf/ : GENERIC_* :general conf file, Grammar is miss. files:
2 Local conf file: Targets/Bonito2F3GNB/conf/ Bonito: contents to compile.
Grammar
option
select
files.*: file that define a module
1 Device depend: files.Bonito2F3GNB
Grammar
define
device
attach
file
2 General: conf/files Makefile.B*
Configure tools: tools/pmoncfg
Memroy management
TLB:
Address space: Physical memory space:256T
Virtual memory space:
User memory space: XUSEG user segment, SR:KSU=10, EXL=0, ERL=0, XTLB reload
Service memory space: SR:KSU=01, EXL=0, ERL=0
Kernel memory space: SR:KSU=00 or EXL=1 or ERL=1 V2P:
异常分类
Reset exception
NMI exception
TLB Refill exception :Non-maskable
Cache errors exception
Generic exception: TLB Invalidation exception, TLB Modification exception
Integer overflow, Trap exception, Syscall exception, Break point, Reserve instructions, Coprocessor unusable, Float coprocessor exception,Bus errors
中断路由:3a有32个外部中断源,每个中断源都有一个8位的路由寄存器Entry。高4位标志ip,低4位对应的cpu 核。
/* Route the LPC interrupt to Core0 INT0 ,对应 Cp0_Status 的 IP2*/
*(volatile unsigned char*)0x900000003ff0140a = 0x11;
0x11为0001 0001表示core0, ip0
// In eic mode ipl is interrupt priority level, ripl is Requested Interrupt Priority Level
中断使能: 三个设置查看寄存器。
中断过程:
外部中断请求
cpu 设置Cause 的excode 和ip。excode 0表示中断。 ip7-ip2表明6个硬件中断源.ip7是timer,ip2 uart or lpc ,ip3 ht, ip6 ipi, 对应core的ip0-3 ip1-0是中断。 之后架构相关部分会判断具体的处理程序入口,应该是硬件完成的。其中0号异常即中断使用通用异常入口0x80000180 expect_vec3_generic(), 之后根据excode 进入具体处理函数,0号异常处理函数是handle_int()。之后根据cause的ip7-0判断中断源。调用相应的处理函数比如8259a 和 timer的处理函数。如果是8259a的话,要读取8259a的到中断号。之后用中断号定位irq_desc.
x86 与mips 中断过程对比
x86: 三个数组idt, irq_desc, vector_irq.
外设通过8259a发来中断向量(通常配置8259a处理方式为中断号+32),定位idt,找到相应处理程序。如果是异常通常在这里程序就结束了。如果是中断要调用do_irq,do_irq通过vector_irq把中断向量转为中断号。用中断号去定位irq_desc,找到action执行。
mips:一个寄存器cause,两个数组 exception_handlers, irqdesc
外设通过8259a发出中断请求,设置cause的 excode和ip位,excode相当与中断向量, exception_hanlers 相当与idt,前者32,后者256(apic的话idt要很大,好象是2400左右,i am not sure)在定位exception_hanlders之前,要选择一个异常地址入口。实际上这个异常地址入口列表加上exception_handlers 就等价于idt了。外部中断的excode为0,定位后跳到expect_vec3_generic(),根据cause的ip位判断中断源,如果是8259a的话,那么和x86最大的区别就是cpu要自己去把中断号读取过来,因为到现在我们还没有涉及到和中断号相关信息,而且前面的excode实际上虽然相当于x86的中断向量,但是不存在像x86那样+32的线性关系。这就没有了x86中断号转换来转换去的麻烦了,但也闲不到。得到中断号就可以去找irq_desc了。剩下就简单了。
1 oxbfc0 0000 is eprom -> Init in ROM start.S
2 Initial serial device UART, maybe for the purpose of debug, I ma not sure.
3 Init memory controller: Through I2c or SMB to get size, tcol, trow informations.
4 Init Cache, TLB: Get cacheline size through config register. godson_init_cache , clean Random data in cache.
5 Build Stack and execution environment.
6 Copy codes of PMON to RAM 0x8010 0000 _start , prepare to excute in RAM ,jump to initmips()
-> Init in RAM, Targets/.../tgt_machdep.c initmips ()
1 Init North bridge
2 Init Sourth Bridge: SMBus, SuperI/O (set and enable serial address, RTC, Keyboard controller), Serial
-> tgt_cpufreq()
-> dbginit() ->tgt_devinit() ->_pci_businit() ->_pci_hwinit()
There are 3 * 64M memory in pci mem are mapped to 0-192M Pci memory by pcimap register.
->_pci_scan_dev()
->init_net()->tgt_devconfig()->pci_devinit()
Enable I/O and Mem space
->configure()
(spl)
Search and match driver and devices.
Copy interrupt handler table, set BEV of SR.
Debug in pmon: PRINTSTR,Stringserial,hexserial,tgt_putchar
Debug in hardware: m, pcicfg, pciscan