Mips cache lock

Maybe mips cache lock is not used as much as cache writeback and cache invalidate,so we need a chance to "learning through practice".

In embedded system,before we have init the RAM,we have no writeable space for stack,but we can use mips cache lock to solve it,lock stack in cache and we can get a small wirteable space for our "C" code.That is what U-Boot do on some mips platform board.

You can see the U-BOOT-SOURCE/cpu/mips/cache.S and U-BOOT-SOURCE/cpu/mips/start.S for detail.It use cache op is 0x1d,reference "See MIPS Run Linux Second Edition" chapter 4,you can know it lock the L1 D-cache.

BTW:In "See MIPS Run Linux Second Edition" Section 4.9.1 The Cache Instruction,third paragraph:
        Of the 5-bit field,the upper 2 bits select which cache to work on
should be:
        Of the 5-bit field,the lower 2 bits select which chache to work on