#define __MAIN__
#define DM9000A
#ifdef __MAIN__
#include "s3c2440.h"
#include <stdarg.h>
#include <stdio.h>
#include <math.h>
#define setb(n) (1<<(n))
//#define ulong unsigned long
//#define uchar unsigned char
typedef unsigned char uchar;
#define uint unsigned int
#ifdef DM9000A
#define rNCR 0x00
#define rGPR 0x1f
#define rNSR 0x01
#define rIMR 0xff
#define rRCR 0x05
#define rISR 0xfe
#define DM9000A_BASE 0x18000000
#define DM9000A_INDEX (*(volatile uchar*)DM9000A_BASE)
#define DM9000A_DATA (*(volatile uchar*)(DM9000A_BASE+0x4))
uchar dm9000a_ior(uchar reg);
void dm9000a(void);
void ydelay(uint n);
#endif
const uint framebuf=0x31000000;
void lcd(void);
void init_ram(void);
void mem_back_set(void* base,uint size,uint dat);
void set_pix(uint x,uint y,uint clr);
void on_print(void);
void init_uart(void){
//initilize uart1
GPHCON=(0x2<<10)|(0x2<<8);
GPHUP=setb(4)|setb(5);//disable pull up
ULCON1=0x00000003;//no perity, 1 stop bit,received or transmitted 8 bit
UCON1=(0x0<<10)|(0x1<<2)|0x1;//using PCLK for uart clk ,and enable tx and rx
UFCON1=(0x3<<6)|(0x3<<4)|(0x1<<2)|(0x1<<1)|0x1;//enable fifo
UMCON1=0;//disable auto flow control
UBRDIV1=26;//baud-rate is 115200 when PCLK is 49.96MHz
}
void putch(uchar d)
{
UTXH1=d;
}
void putstr(char *str)
{
char *p=str;
while(*p!=0)
{
while(UFSTAT1&0x4000);//charge the FIFO buffer is full or not
UTXH1=*(p++);
}
}
#if 1
void printy(char *fmt,...)
{
char buf[1024];
va_list args;
//int n;
//char *p;
va_start(args, fmt);
vsprintf(buf, fmt, args);
va_end(args);
putstr(buf);
}
#endif
int main(void)
{//频率设置到400MHz
int i,j;
char buf[256];
// MPLLCON = 0x0005C011;
WTCON=0;
GPBCON= GPBCON&0xfffffff0|0x5;
GPBDAT = 0X00000000;
ADCCON = setb(14)|(255<<6)|(0<<3)|1;
init_uart();
init_ram();
lcd();
on_print();
mem_back_set((void*)framebuf,320*80,0xff0000);
mem_back_set((void*)(framebuf+(320*80*4)),320*80,0x00ff00);
mem_back_set((void*)(framebuf+(320*160*4)),320*80,0x0000ff);
//dm9000a();
while(1)
{
i=ADCCON;
for(i = 5;i > 0;i--);
//putch('y');
//printy("yaoya:%d",i);
//putstr(buf);
if(GPBDAT&0x1)GPBDAT&=~0x00000003;
else GPBDAT|=0x00000003;
ADCCON|=1;
i=0;
j=7;
while(j>=0)
{
ADCCON = setb(14)|(255<<6)|(j<<3)|1;
while(!(ADCCON&0x8000))i++;
i=ADCDAT0&0x3ff;
printy("adc %d:%d\n",j,i);
j--;
}
if(UTRSTAT1&0x1)
{
i=0;
while(UTRSTAT1&0x1)buf[i++]=URXH1;
buf[i]=0;
printy("received: %s\n",buf);
}
}
}
#ifdef DM9000A
uchar dm9000a_ior(uchar reg)
{
DM9000A_INDEX=reg;
return DM9000A_DATA;
}
void dm9000a_iow(uchar dat,uchar reg)
{
DM9000A_INDEX=reg;
DM9000A_DATA=dat;
}
void ydelay(uint n)
{
uchar tmp;
while(n--)
{
tmp=255;
while(tmp--);
}
}
void dm9000a(void)
{
unsigned short id;
id = dm9000a_ior(0x28) | (dm9000a_ior(0x29)<<8);
printy("read dm9000 vid = 0x%x\n", id);
id = dm9000a_ior(0x2a) | (dm9000a_ior(0x2b)<<8);
printy("read dm9000 pid = 0x%x\n", id);
id = dm9000a_ior(0x8) | (dm9000a_ior(0x9)<<8);
printy("read dm9000 reg(0x09,0x08) = 0x%x\n", id);
printy("dm9000 isr = 0x%x\n", dm9000a_ior(0xfe));
//start phy
dm9000a_iow(dm9000a_ior(rGPR)&0xfe,rGPR);
printy("dm9000 rGPR = 0x%x\n",dm9000a_ior(rGPR));
//reset 2 times
dm9000a_iow((dm9000a_ior(rNCR)&0xf8)|0x3,rNCR);
ydelay(10);
dm9000a_iow(dm9000a_ior(rNCR)&0xf8,rNCR);
dm9000a_iow((dm9000a_ior(rNCR)&0xf8)|0x3,rNCR);
ydelay(10);
dm9000a_iow(dm9000a_ior(rNCR)&0xf8,rNCR);
printy("dm9000 rNCR = 0x%x\n",dm9000a_ior(rNCR));
//normal mode
dm9000a_iow(dm9000a_ior(rNCR)&0xf9,rNCR);
printy("dm9000 rNCR = 0x%x\n",dm9000a_ior(rNCR));
//clear the state of sent
dm9000a_iow(dm9000a_ior(rNSR)|0x2c,rNSR);
printy("dm9000 rNSR = 0x%x\n",dm9000a_ior(rNSR));
//bit[7]=1:RX/TX buffer pointer can auto areace
dm9000a_iow(dm9000a_ior(rIMR)|0x83,rIMR);
printy("dm9000 rIMR = 0x%x\n",dm9000a_ior(rIMR));
//enable receive data
dm9000a_iow(dm9000a_ior(rRCR)|0x01,rRCR);
printy("dm9000 rRCR = 0x%x\n",dm9000a_ior(rRCR));
printy("dm9000 rISR = 0x%x\n",dm9000a_ior(rISR));
while(1)
{
ydelay(10);
if(dm9000a_ior(rISR))
{
printy("dm9000 rISR = 0x%x\n",dm9000a_ior(rISR));
dm9000a_iow(0x0,rISR);
printy("received data 0x%x\n",dm9000a_ior(rISR));
}
}
}
#endif
void lcd(void)
{
#define LCD_WIDTH 320
#define LCD_HEIGHT 240
#define HPW 30
#define HBP 38
#define HFP 20
#define VPW 3
#define VBP 15
#define VFP 4
//uint clkval=399650000/(4*320*240*24*2)-1;
//CLKCON&=(~(1<<5));
CLKCON|=(1<<5);
GPCUP=0xffffffff; // Disable Pull-up register
GPCCON=0xaaaaaaaa; //Initialize VD[7:0],LCDVF[2:0],VM,VFRAME,VLINE,VCLK,LEND
GPDUP=0xffffffff; // Disable Pull-up register
GPDCON=0xaaaaaaaa; //Initialize VD[23:8]
GPGUP|=(1<<4);
GPGCON|=(3<<8);
LCDCON1=(8<<8)|(3<<5)|(0xd<<1)|0;
LCDCON2=((VBP-1)<<24)|((LCD_HEIGHT-1)<<14)|((VFP-1)<<6)|VPW;
LCDCON3=((HBP-1)<<19)|((LCD_WIDTH-1)<<8)|(HFP-1);
LCDCON4=(HPW-1);
LCDCON5=(1<<9)|(1<<8)|(1<<3);
LCDSADDR1=((framebuf>>22)<<21)|((framebuf>>1)&0x1fffff);
LCDSADDR2=((framebuf+LCD_WIDTH*LCD_HEIGHT*4)>>1)&0x1fffff;
LCDSADDR3=(/*(340*2)*/0<<11)|(LCD_WIDTH*2);
TPAL=0;
LCDINTPND=0;
LCDSRCPND=0;
LCDINTMSK=3;
LPCSEL&=(~7);
LCDCON1|=1;
printy("LCDSADDR1=0x%x\nLCDSADDR2=0x%x\nLCDSADDR3=0x%x\n",
LCDSADDR1,LCDSADDR2,LCDSADDR3);
}
void init_ram(void)
{
volatile uint *p=(uint*)0x31000000;
int size=0x400000;
uint clr=0;
while(size--)
{
*(p++)=clr;
clr+=4;
//if(clr>0xffffff)clr=0;
}
}
void mem_back_set(void* base,uint size,uint dat)
{
volatile int *p=(int*)base;
int *to=(int*)(p+size);
while(p<to)*(p++)=dat;
}
void set_pix(uint x,uint y,uint clr)
{
volatile uint*p=(uint*)framebuf;
p[y*320+x]=clr;
}
void on_print(void)
{
uint ox,oy;
float r,angle=0.5,pi2=3.1416*2;
ox=160;
oy=120;
r=50.0;
for(angle=0;angle<pi2;angle=angle+0.01)
{
set_pix((uint)(cos(angle)*r+ox),(uint)(sin(angle)*r+oy),0xff0000);
}
}
#endif //__MAIN__
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