CMOS Inverter

A number of other important properties of static CMOS can be derived from this switch level view:
• The high and low output levels equal VDD and GND, respectively; in other words,
the voltage swing is equal to the supply voltage. This results in high noise margins.
• The logic levels are not dependent upon the relative device sizes, so that the transistorscan be minimum size. Gates with this property are called ratioless. This is incontrast with ratioed logic, where logic levels are determined by the relative dimensions of the composing transistors.
• In steady state, there always exists a path with finite resistance between the output and either VDD or GND. A well-designed CMOS inverter, therefore, has a low output impedance, which makes it less sensitive to noise and disturbances. Typical values of the output resistance are in kW range.
• The input resistance of the CMOS inverter is extremely high, as the gate of an MOS transistor is a virtually perfect insulator and draws no dc input current. Since the input node of the inverter only connects to transistor gates, the steady-state input current is nearly zero. A single inverter can theoretically drive an infinite number of gates (or have an infinite fan-out) and still be functionally operational; however, increasing the fan-out also increases the propagation delay, as will become clear below. So, although fan-out does not have any effect on the steady-state behavior, it degrades the transient response.

• No direct path exists between the supply and ground rails under steady-state operating conditions (this is, when the input and outputs remain constant). The absence of current flow (ignoring leakage currents) means that the gate does not consume any static power.