mx51调试（四）之uart

    根据mx51的data sheet第59章的uart部分说明，设置和初始化uart模块。

  看第2章uart在cpu memory map的基地址：

  Start Address End Address Size Region

  73FB_C000 73FB_FFFF 16K UART 1
  73FC_0000 73FC_3FFF 16K UART 2

   看第59章主要的寄存器的偏移地址定义：

   Table 59-3. UART Memory MapOffset Address (Register Abbreviation)
Register Access Reset Value Section/Page
0x0000 (URXD) UART Receiver Register R 00– – 59.3.3.1/59-10
0x0004–0x003c Reserved — — —
0x0040 (UTXD) UART Transmitter Register W 00– – 59.3.3.2/59-12
0x0044–0x007c Reserved — — —
0x0080 (UCR1) UART Control Register 1 R/W 0000 59.3.3.3/59-13
0x0084 (UCR2) UART Control Register 2 R/W 0001 59.3.3.4/59-15
0x0088 (UCR3) UART Control Register 3 R/W 0700 59.3.3.5/59-17
0x008c (UCR4) UART Control Register 4 R/W 8000 59.3.3.6/59-19
0x0090 (UFCR) UART FIFO Control Register R/W 0801 59.3.3.7/59-21
0x0094 (USR1) UART Status Register 1 R/W 2040 59.3.3.8/59-22
0x0098 (USR2) UART Status Register 2 R/W 4028 59.3.3.9/59-24
0x009c (UESC) UART Escape Character Register R/W 002b 59.3.3.10/59-27
0x00a0 (UTIM) UART Escape Timer Register R/W 0000 59.3.3.11/59-27
0x00a4 (UBIR) UART BRM Incremental Register R/W 0000 59.3.3.12/59-28
0x00a8 (UBMR) UART BRM Modulator Register R/W 0000 59.3.3.13/59-29
0x00ac (UBRC) UART Baud Rate Count Register R 0004 59.3.3.14/59-30
0x00b0 (ONEMS) UART One Millisecond Register R/W 000000 59.3.3.15/59-31
0x00b4 (UTS) UART Test Register R/W 0060 59.3.3.16/59-32

   看给出的事例代码：

 

   The following example sequence can be used to program the UART in order to send and receive characters
in RS-232 mode.
The assumptions are as follows:
• Input UART clock = 100 MHz
• Baud rate = 921.6 Kbps
• Data bits = 8 bits
• Parity = Even
• Stop bits = 1 bit
• Flow control = Hardware
Main program:
1. UCR1 = 0x0001
Enable the UART.
2. UCR2 = 0x2127
Set hardware flow control, data format and enable transmitter and receiver.
3. UCR3 = 0x0704
Set UCR3[RXDMUXSEL] = 1.
4. UCR4 = 0x7C
Set CTS trigger level to 31,
5. UFCR = 0x089E
Set internal clock divider = 5 (divide input UART clock by 5). So the reference clock is 100
MHz ÷ 5 = 20MHz.
Set TXTL = 2 and RXTL = 30.
6. UBIR = 0x08FF
7. UBMR = 0x0C34
In the above two steps, set baud rate to 921.6 Kbps based on the 20 MHz reference clock.
8. UCR1 = 0x2201
Enable the TRDY and RRDY interrupts.
Interrupt service routine for the transmitter:
• Write characters into UTXDThe TRDY interrupt is automatically de-asserted when the data level of the TxFIFO exceeds the
TXTL = 2. Note that the first time, the interrupt may be de-asserted after four characters are written into
the TxFIFO because of the shift register.
Interrupt service routine for the receiver:
• Read characters from URXD
The RRDY interrupt will be automatically de-asserted when the data level of the RxFIFO is below the
RXTL = 30.

 

在jlink中的调试代码为：

 w4 0x73fbc080,0x0001

 w4 0x73fbc084,0x2127

 w4 0x73fbc088,0x0704

 w4 0x73fbc08c,0x7c

 w4 0x73fbc090,0x089e

 w4 0x73fbc0a4,0x08ff

 w4 0x73fbc0a8,0x0c34

 w4 0x73fbc080,2201

 在linux中编程的汇编代码为：

#sdram_init.S
.global _start

_start:
        ldr r0,=0x73fbc080
        ldr r1,=0x0001
        str r0,[r1]

        ldr r0,=0x73fbc084
        ldr r1,=0x2127
        str r0,[r1]

        ldr r0,=0x73fbc088
        ldr r1,=0x0704
        str r0,[r1]

        ldr r0,=0x73fbc08c
        ldr r1,=0x7c
        str r0,[r1]

        ldr r0,=0x73fbc090
        ldr r1,=0x089e
        str r0,[r1]

        ldr r0,=0x73fbc0a4
        ldr r1,=0x08ff
        str r0,[r1]

        ldr r0,=0x73fbc0a8
        ldr r1,=0x0c34
        str r0,[r1]

        ldr r0,=0x73fbc080
        ldr r1,=0x2201
        str r0,[r1]

  然后通过编译成bin文件：

  arm-linux-gcc -c sdram_init.S

  arm-linux-ld -Ttext 0x90000000 sdram_init.o -Map boot.map -o boot.elf

  arm-linux-objcopy -O binary boot.elf boot.bin

  再在jlink中加到内存0x90000000处执行：

  loadbin c:\boot.bin,0x90000000

  g

  完结。