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CC2530的DMA控制器编程分析

分类： 嵌入式

2013-11-07 14:46:01

    CC2530 DMA控制器操作流程图如下：
    
    CC2530中不能用设置寄存器的方式配置DMA的参数，而要使用一种特殊的DMA配置结构体，DMA Configuration Data Structure结构体，IAR编译环境中位域字段默认取向采用小端模式，配置结构体声明前使用#pragma bitfields=reversed取反向，声明结束后恢复IAR默认方式。

DMA配置结构体：

  1. // Place the bitfield members from the most significant bit to the least significant bit.
  2. #pragma bitfields=reversed
  3. typedef struct {
  4.    uint8 SRCADDRH;            //源地址高字节
  5.    uint8 SRCADDRL;            //源地址低字节
  6.    uint8 DESTADDRH;           //目的地址高字节
  7.    uint8 DESTADDRL;           //目的地址低字节
  8.    uint8 VLEN : 3;            //变长传输模式选择
  9.    uint8 LENH : 5;            //传输长度高字节
  10.    uint8 LENL : 8;            //传输长度低字节
  11.    uint8 WORDSIZE : 1;        //字节传输或字传输
  12.    uint8 TMODE : 2;           //传输模式选择
  13.    uint8 TRIG : 5;            //触发时间选择
  14.    uint8 SRCINC : 2;          //源地址增量方式选择
  15.    uint8 DESTINC : 2;         //目的地址增量方式选择
  16.    uint8 IRQMASK : 1;         //中断屏蔽位
  17.    uint8 M8 : 1;              //字节传输模式时用，8或7 bit传输长度
  18.    uint8 PRIORITY : 2;        //优先级选择
  19. } DMA_DESC;
  20. #pragma bitfields=default
    根据CC253x编程手册中的相关介绍：
    DMA共有四种传输模式
    单次传输模式：触发条件发生后启动一次传输，接着DMA通道等待下次触发发生。当传输长度字段指定的传输次数完成后，设置中断标志位通知CPU并卸载DMA通道配置参数。
    块传输模式：触发条件发生后，尽快完成长度字段指定的传输次数，完成后通知CPU并卸载DMA通道配置参数，即执行DMAARMn = 0。
    重复单次传输模式：与单次模式前段相同，只是会重装通道配置参数。
    重复块传输模式：与块模式前段相同，只是会重装通道配置参数。
    四种方式的差别具体看上边DMA操作流程图。

    DMA编程流程：
    1.DMA配置结构体赋值
    2.将配置结构体内存地址赋值给DMAxCFGH:DMAxCFGL
    3.DMAARMx相应通道位置1，装载通道配置参数，根据手册要求，装载通道时需要延迟9个时钟周期使其生效
    4.手动触发或等待触发条件
    5.清除中断标志位，无论中断屏蔽位关闭与否，传输完成后相应中断标志位都会置位

     CC2541_43_44_45_Peripherals_Software_Examples中DMA例程分析

dma_man_trigger.c 该例程展示了如何手动触发DMA，使用DMA方式复制内存数据到内存其他区域中

  1. /*******************************************************************************
  2.   Filename: dma_man_trigger.c

  4.   Description: This example shows how to trigger the DMA manually and use
  5.                DMA to move data from one area of RAM to another.

  7. *******************************************************************************/

  9. /*******************************************************************************
  10. * INCLUDES
  11. */

  13. // Include Name definitions of individual bits and bit-fields in the CC254x device registers.
  14. #include <ioCC254x_bitdef.h>
  15. #include <hal_types.h>
  16. #include <dma.h>
  17. // Include device specific file
  18. #include "ioCC2530.h"


  21. /*******************************************************************************
  22. * CONSTANTS
  23. */

  25. // String length.
  26. #define DATA_AMOUNT 16


  29. /*******************************************************************************
  30. * LOCAL VARIABLES
  31. */

  33. // The data that is to be copied to another place in memory.
  34. static char data[DATA_AMOUNT] = "DMA man trigger!";

  36. // The area where the data is to be copied to.
  37. static char copy[DATA_AMOUNT];

  39. // DMA configuration descriptor used for memory copy.
  40. static DMA_DESC dmaConfig0;


  43. /*******************************************************************************
  44. * LOCAL FUNCTIONS
  45. */


  48. /*******************************************************************************
  49. * @fn main
  50. *
  51. * @brief Sets up the DMA configuration struct, saves its address, arms the
  52. * DMA channel and triggers it manually. After the DMA transfer is
  53. * complete, the DMA channel 0 interrupt flag is cleared (it is
  54. * automatically set).
  55. *
  56. * @param void
  57. *
  58. * @return void
  59. *******************************************************************************/
  60. void main(void)
  61. {
  62.     /* Configure DMA channel 0. Settings:
  63.      * SRCADDR: address of the data to be copied (increasing).
  64.      * DESTADDR: address the data will be copied to (increasing).
  65.      * VLEN: use LEN for transfer count.
  66.      * LEN: equal to the number of bytes to be transferred.
  67.      * WORDSIZE: each transfer should transfer one byte.
  68.      * TMODE: block mode.
  69.      * TRIG: let the DMA channel be triggered manually, i.e., by setting the
  70.      * [DMAREQ.DMAREQ0] bit.
  71.      * SRCINC: increment by one byte.
  72.      * DESTINC: increment by one byte.
  73.      * IRQMASK: disable interrupts from this channel.
  74.      * M8: 0, irrelevant since we use LEN for transfer count.
  75.      * PRIORITY: high.
  76.      */
  77.     dmaConfig0.SRCADDRH = ((uint16)data >> 8) & 0x00FF;
  78.     dmaConfig0.SRCADDRL = (uint16)data & 0x00FF;
  79.     dmaConfig0.DESTADDRH = ((uint16)copy >> 8) & 0x00FF;
  80.     dmaConfig0.DESTADDRL = (uint16)copy & 0x00FF;
  81.     dmaConfig0.VLEN = DMA_VLEN_USE_LEN;             //使用固定长度
  82.     dmaConfig0.LENH = (DATA_AMOUNT >> 8) & 0x00FF;
  83.     dmaConfig0.LENL = DATA_AMOUNT & 0x00FF;        
  84.     dmaConfig0.WORDSIZE = DMA_WORDSIZE_BYTE;        //字节传输
  85.     dmaConfig0.TMODE = DMA_TMODE_BLOCK;             //块传输方式
  86.     dmaConfig0.TRIG = DMA_TRIG_NONE;                //手动触发
  87.     dmaConfig0.SRCINC = DMA_SRCINC_1;
  88.     dmaConfig0.DESTINC = DMA_DESTINC_1;
  89.     dmaConfig0.IRQMASK = DMA_IRQMASK_DISABLE;       //关闭DMA中断方式
  90.     dmaConfig0.M8 = DMA_M8_USE_8_BITS;
  91.     dmaConfig0.PRIORITY = DMA_PRI_HIGH;

  93.     /* The DMA configuration data structure may reside at any location in
  94.      * unified memory space, and the address location is passed to the DMA
  95.      * through DMA0CFGH:DMA0CFGL.
  96.      */
  97.     DMA0CFGH = ((uint16)&dmaConfig0 >> 8) & 0x00FF;
  98.     DMA0CFGL = (uint16)&dmaConfig0 & 0x00FF;

  100.     /* Arm the DMA channel, so that a DMA trigger can initiate DMA writing,
  101.     and apply 9 NOPs to allow the DMA arming to actually take effect. */
  102.     DMAARM |= DMAARM_DMAARM0;
  103.     NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP(); // 9 NOPs

  105.     // Trigger the DMA channel manually.
  106.     DMAREQ |= DMAREQ_DMAREQ0;

  108.     // Wait for the DMA transfer to complete.
  109.     while ( !(DMAIRQ & DMAIRQ_DMAIF0) );

  111.     /* By now, the transfer is completed, so the transfer count is reached.
  112.      * The DMA channel 0 interrupt flag is then set, so we clear it here.
  113.      */
  114.     
  115.     // Clear interrupt flag by R/W0, see datasheet.
  116.     DMAIRQ = ~DMAIRQ_DMAIF0;
  117.     
  118.     // End function with infinite loop (for debugging purposes).
  119.     while(1);
  120. }

dma_pre_trigger.c 通道0采用手动触发方式，通道1追踪通道0完成时触发

  1. /*******************************************************************************
  2.   Filename: dma_prev_trigger.c

  4.   Description: This example shows both how to trigger a DMA channel manually and
  5.                how to trigger a DMA channel by the completion of the previous
  6.                channel. Both channels copy data in RAM. Channel 0 makes the
  7.                first copy and channel 1 makes a copy of the first copy.


  10. *******************************************************************************/

  12. /*******************************************************************************
  13. * INCLUDES
  14. */

  16. // Include Name definitions of individual bits and bit-fields in the CC254x device registers.
  17. #include <ioCC254x_bitdef.h>
  18. #include <hal_types.h>
  19. #include <dma.h>
  20. // Include device specific file
  21. #include "ioCC2530.h"

  23. /*******************************************************************************
  24. * CONSTANTS
  25. */

  27. // String length.
  28. #define DATA_AMOUNT 16


  31. /*******************************************************************************
  32. * LOCAL VARIABLES
  33. */

  35. // The data that is to be copied to another place in memory.
  36. static char data[DATA_AMOUNT] = "DMA prev trigger";

  38. // The araes where data is to be copied to.
  39. static char copy1[DATA_AMOUNT];
  40. static char copy2[DATA_AMOUNT];

  42. // DMA configuration descriptor used for memory copy.
  43. static DMA_DESC dmaConfig0, dmaConfig1;


  46. /*******************************************************************************
  47. * LOCAL FUNCTIONS
  48. */


  51. /*******************************************************************************
  52. * @fn main
  53. *
  54. * @brief Sets up DMA configuration structs for both channel 0 and 1, saves
  55. * their addresses, arms both DMA channels and triggers channel 0
  56. * manually. After the first DMA transfer is completed, the DMA
  57. * channel 0 interrupt flag is cleared (it is automatically set).
  58. * The completion of the channel 0 transfer triggers the transfer on
  59. * channel 1, which copies the same data yet again. After the second
  60. * DMA transfer is completed, the DMA channel 0 interrupt flag is
  61. * also cleared and the program terminates.
  62. *
  63. * @param void
  64. *
  65. * @return void
  66. *******************************************************************************/
  67. void main(void)
  68. {
  69.     /* Configure DMA channel 0. Settings:
  70.      * SRCADDR: address of the data to be copied (increasing).
  71.      * DESTADDR: address the data will be copied to (increasing).
  72.      * VLEN: use LEN for transfer count.
  73.      * LEN: equal to the number of bytes to be transferred.
  74.      * WORDSIZE: each transfer should transfer one byte.
  75.      * TMODE: block mode.
  76.      * TRIG: let the DMA channel be triggered manually, i.e., by setting the
  77.      * [DMAREQ.DMAREQ0] bit.
  78.      * SRCINC: increment by one byte.
  79.      * DESTINC: increment by one byte.
  80.      * IRQMASK: disable interrupts from this channel.
  81.      * M8: 0, irrelevant since we use LEN for transfer count.
  82.      * PRIORITY: high.
  83.      */
  84.     dmaConfig0.SRCADDRH = ((uint16)data >> 8) & 0x00FF;
  85.     dmaConfig0.SRCADDRL = (uint16)data & 0x00FF;
  86.     dmaConfig0.DESTADDRH = ((uint16)copy1 >> 8) & 0x00FF;
  87.     dmaConfig0.DESTADDRL = (uint16)copy1 & 0x00FF;
  88.     dmaConfig0.VLEN = DMA_VLEN_USE_LEN;
  89.     dmaConfig0.LENH = (DATA_AMOUNT >> 8) & 0x00FF;
  90.     dmaConfig0.LENL = DATA_AMOUNT & 0x00FF;
  91.     dmaConfig0.WORDSIZE = DMA_WORDSIZE_BYTE;
  92.     dmaConfig0.TMODE = DMA_TMODE_BLOCK;
  93.     dmaConfig0.TRIG = DMA_TRIG_NONE;
  94.     dmaConfig0.SRCINC = DMA_SRCINC_1;
  95.     dmaConfig0.DESTINC = DMA_DESTINC_1;
  96.     dmaConfig0.IRQMASK = DMA_IRQMASK_DISABLE;
  97.     dmaConfig0.M8 = DMA_M8_USE_8_BITS;
  98.     dmaConfig0.PRIORITY = DMA_PRI_HIGH;

  100.     /* Configure DMA channel 1. Settings:
  101.      * Same as for channel 0, except for different source and destination
  102.      * addresses and let the DMA channel be triggered by the completion of the
  103.      * previous channel.
  104.      */
  105.     dmaConfig1.SRCADDRH = ((uint16)copy1 >> 8) & 0x00FF;
  106.     dmaConfig1.SRCADDRL = (uint16)copy1 & 0x00FF;
  107.     dmaConfig1.DESTADDRH = ((uint16)copy2 >> 8) & 0x00FF;
  108.     dmaConfig1.DESTADDRL = (uint16)copy2 & 0x00FF;
  109.     dmaConfig1.VLEN = DMA_VLEN_USE_LEN;
  110.     dmaConfig1.LENH = (DATA_AMOUNT >> 8) & 0x00FF;
  111.     dmaConfig1.LENL = DATA_AMOUNT & 0x00FF;
  112.     dmaConfig1.WORDSIZE = DMA_WORDSIZE_BYTE;
  113.     dmaConfig1.TMODE = DMA_TMODE_BLOCK;
  114.     dmaConfig1.TRIG = DMA_TRIG_PREV;        //前一个通道传输完成触发该通道
  115.     dmaConfig1.SRCINC = DMA_SRCINC_1;
  116.     dmaConfig1.DESTINC = DMA_DESTINC_1;
  117.     dmaConfig1.IRQMASK = DMA_IRQMASK_DISABLE;
  118.     dmaConfig1.M8 = DMA_M8_USE_8_BITS;
  119.     dmaConfig1.PRIORITY = DMA_PRI_HIGH;

  121.     /* The DMA configuration data structures may reside at any location in
  122.      * unified memory space, and the address locations is passed to the DMA
  123.      * through DMA0CFGH:DMA0CFGL and DMA1CFGH:DMA1CFGL for channel 0 and 1,
  124.      * respectively.
  125.      */
  126.     DMA0CFGH = ((uint16)&dmaConfig0 >> 8) & 0x00FF;
  127.     DMA0CFGL = (uint16)&dmaConfig0 & 0x00FF;
  128.     DMA1CFGH = ((uint16)&dmaConfig1 >> 8) & 0x00FF;
  129.     DMA1CFGL = (uint16)&dmaConfig1 & 0x00FF;

  131.     /* Arm DMA channel 0 and 1, so that they can be triggered by their
  132.        respective triggers, and apply 18 NOPs to allow the DMA arming
  133.        to actually take effect. */
  134.     DMAARM |= (DMAARM_DMAARM0 | DMAARM_DMAARM1);
  135.     NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP(); // 9 NOPs //装载通道的延时时间随装载通道数累加
  136.     NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP();NOP(); // 9 NOPs

  138.     // Trigger the DMA channel 0 manually.
  139.     DMAREQ |= DMAREQ_DMAREQ0;

  141.     // Wait for DMA transfer on channel 0 to complete.
  142.     while ( !(DMAIRQ & DMAIRQ_DMAIF0) );

  144.     /* By now, the first transfer is completed. The DMA channel 0 interrupt flag
  145.      * is then set, so we clear it here.
  146.      */
  147.     
  148.     // Clear interrupt flag by R/W0, see datasheet.
  149.     DMAIRQ = ~DMAIRQ_DMAIF0;

  151.     /* Wait for DMA transfer on channel 1 to complete. Then clear its interrupt
  152.      * flag.
  153.      */
  154.     
  155.     while ( !(DMAIRQ & DMAIRQ_DMAIF1) );
  156.     // Clear interrupt flag by R/W0, see datasheet.
  157.     DMAIRQ = ~DMAIRQ_DMAIF1;

  159.     // End function with infinite loop (for debugging purposes).
  160.     while(1);
  161. }
    调试时将断点打在DMAREQ |= DMAREQ_DMAREQ0;处，观察数组内存值的变化，可以看到，只要执行该条语句，两个通道的DMA操作接连完成，中断标志位都置位了，while ( !(DMAIRQ & DMAIRQ_DMAIF0) )；及后续指令无需等到。

已经将平台修改为CC2530，源代码附件
dma.zip

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