在前面实验的基础上.增加了初始化存储控制器的13个寄存器的操作.
两个汇编文件＋一个C语言文件 C语言文件可以是先前实验的任何一个.
start.S
#define SDRAM_BASE 0x30000000
#define WATCHDOG 0x53000000
#define BWSCON 0x48000000
.text
.global _start
_start:
bl disable_watchdog
bl sdram_init
bl copy_to_sdram
ldr pc, =on_sdram
on_sdram:
ldr sp, =0x34000000
bl main
halt:
b halt
disable_watchdog:
ldr r0, =WATCHDOG
mov r1, #0
str r1, [r0]
mov pc, lr
copy_to_sdram:
ldr r0, =SDRAM_BASE
mov r1, #0
add r2, r1, #1024*4
0:
ldr r3, [r1], #4
str r3, [r0], #4
cmp r1, r2
bne 0b
mov pc, lr
lowlevel_init.S 借鉴的U－BOOT, 稍微修改了几个参数.
#define BWSCON 0x48000000
/* BWSCON */
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW16)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
/* BANK0CON */
#define B0_Tacs 0x0 /* 0clk */
#define B0_Tcos 0x0 /* 0clk */
#define B0_Tacc 0x7 /* 14clk */
#define B0_Tcoh 0x0 /* 0clk */
#define B0_Tah 0x0 /* 0clk */
#define B0_Tacp 0x0
#define B0_PMC 0x0 /* normal */
/* BANK1CON */
#define B1_Tacs 0x0 /* 0clk */
#define B1_Tcos 0x0 /* 0clk */
#define B1_Tacc 0x7 /* 14clk */
#define B1_Tcoh 0x0 /* 0clk */
#define B1_Tah 0x0 /* 0clk */
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
/* what's special with Bank3 */
#define B3_Tacs 0x0 /* 0clk */
#define B3_Tcos 0x0 /* 4clk */
#define B3_Tacc 0x7 /* 14clk */
#define B3_Tcoh 0x0 /* 1clk */
#define B3_Tah 0x0 /* 0clk */
#define B3_Tacp 0x0 /* 6clk */
#define B3_PMC 0x0 /* normal */
#define B4_Tacs 0x0 /* 0clk */
#define B4_Tcos 0x0 /* 0clk */
#define B4_Tacc 0x7 /* 14clk */
#define B4_Tcoh 0x0 /* 0clk */
#define B4_Tah 0x0 /* 0clk */
#define B4_Tacp 0x0
#define B4_PMC 0x0 /* normal */
#define B5_Tacs 0x0 /* 0clk */
#define B5_Tcos 0x0 /* 0clk */
#define B5_Tacc 0x7 /* 14clk */
#define B5_Tcoh 0x0 /* 0clk */
#define B5_Tah 0x0 /* 0clk */
#define B5_Tacp 0x0
#define B5_PMC 0x0 /* normal */
#define B6_MT 0x3 /* SDRAM */
#define B6_Tacc 0x7
#define B6_Trcd 0x1
#define B6_SCAN 0x1 /* 9bit */
#define B7_MT 0x3 /* SDRAM */
#define B7_Tacc 0x7
#define B7_Trcd 0x1 /* 3clk */
#define B7_SCAN 0x1 /* 9bit */
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x0 /* 2clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x2 /* 3clk */
#define REFCNT 1955 /* period=64/8192 us, HCLK=12Mhz */
.global sdram_init
sdram_init:
adrl r0, SMRDATA
ldr r1, =BWSCON
add r2, r0, #13*4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r0, r2
bne 0b
mov pc, lr
.align 4
SMRDATA:
.long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
.long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
.long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
.long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
.long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
.long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
.long ((B6_MT<<15)+(B6_Tacc<<8)+(B6_Trcd<<2)+(B6_SCAN))
.long ((B7_MT<<15)+(B7_Tacc<<8)+(B7_Trcd<<2)+(B7_SCAN))
.long (0x8c0000+REFCNT)
.long 0x00000031
.long 0x00000030
.long 0x00000030
Makefile
CROSS_COMPILE := arm-linux-
CC := $(CROSS_COMPILE)gcc
CPP := $(CROSS_COMPILE)gcc -E
AS := $(CROSS_COMPILE)as
LD := $(CROSS_COMPILE)ld
OBJCOPY := $(CROSS_COMPILE)objcopy
all:u-boot.bin
u-boot.bin: test_elf
$(OBJCOPY) -O binary -S $< $@
test_elf: start.o lowlevel_init.o main.o
$(LD) -Ttext 0x30000000 -o $@ start.o lowlevel_init.o main.o
.S.s:
$(CPP) -o $@ $<
.s.o:
$(AS) -o $@ $<
.c.o:
$(CC) -c -o $@ $<
.PHONY clean:
clean:
rm -f *.s *.o *.bin test_elf
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