全部博文(75)
分类: 嵌入式
2009-11-07 15:48:07
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int s3c2410_dma_enqueue(unsigned int channel, void *id,
dma_addr_t data, int size)
发起一次dma传输
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static void init_s3c2410_iis_bus_rx(void)
{
unsigned int iiscon, iismod, iisfcon;
char *dstr;
DPRINTK("init_s3c2410_iis_bus_rx\n");
//Kill everything...
writel(0, iis_base + S3C2410_IISPSR);
writel(0, iis_base + S3C2410_IISCON);
writel(0, iis_base + S3C2410_IISMOD);
writel(0, iis_base + S3C2410_IISFCON);
clk_enable(iis_clock);
iiscon = iismod = iisfcon = 0;
//Setup basic stuff
iiscon |= S3C2410_IISCON_PSCEN; // Enable prescaler
iismod |= S3C2410_IISMOD_MASTER; // Set interface to Master Mode
iismod |= S3C2410_IISMOD_LR_LLOW; // Low for left channel
iismod |= S3C2410_IISMOD_MSB; // IIS format
iismod |= S3C2410_IISMOD_16BIT; // Serial data bit/channel is 16 bit
iismod |= S3C2410_IISMOD_384FS; // Master clock freq = 384 fs
iismod |= S3C2410_IISMOD_32FS; // 32 fs
iisfcon|= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE; //Set RX FIFO acces mode to DMA
//iisfcon|= S3C2410_IISFCON_TXDMA; //Set RX FIFO acces mode to DMA
iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN; //Enable RX DMA service request
//iiscon |= S3C2410_IISCON_TXIDLE; //Set TX channel idle
iiscon &= (~S3C2410_IISCON_RXIDLE);
iismod |= S3C2410_IISMOD_RXMODE; //Set RX Mode
iismod |= S3C2410_IISMOD_TXMODE;
dstr="RX";
//setup the prescaler
audio_set_dsp_speed(audio_rate);
//iiscon has to be set last - it enables the interface
writel(iismod, iis_base + S3C2410_IISMOD);
writel(iisfcon, iis_base + S3C2410_IISFCON);
writel(iiscon, iis_base + S3C2410_IISCON);
}
static void init_s3c2410_iis_bus_tx(void)
{
unsigned int iiscon, iismod, iisfcon;
char *dstr;
DPRINTK("init_s3c2410_iis_bus_tx\n");
//Kill everything...
writel(0, iis_base + S3C2410_IISPSR);
writel(0, iis_base + S3C2410_IISCON);
writel(0, iis_base + S3C2410_IISMOD);
writel(0, iis_base + S3C2410_IISFCON);
clk_enable(iis_clock);
iiscon = iismod = iisfcon = 0;
//Setup basic stuff
iiscon |= S3C2410_IISCON_PSCEN; // Enable prescaler
iismod |= S3C2410_IISMOD_MASTER; // Set interface to Master Mode
iismod |= S3C2410_IISMOD_LR_LLOW; // Low for left channel
iismod |= S3C2410_IISMOD_MSB; // MSB format
iismod |= S3C2410_IISMOD_16BIT; // Serial data bit/channel is 16 bit
iismod |= S3C2410_IISMOD_384FS; // Master clock freq = 384 fs
iismod |= S3C2410_IISMOD_32FS; // 32 fs
iisfcon|= S3C2410_IISFCON_RXDMA; //Set RX FIFO acces mode to DMA
iisfcon|= S3C2410_IISFCON_TXDMA; //Set TX FIFO acces mode to DMA
iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN; //Enable TX DMA service request
//iiscon |= S3C2410_IISCON_RXIDLE; //Set RX channel idle
iiscon &= ~S3C2410_IISCON_TXIDLE;
iismod |= S3C2410_IISMOD_TXMODE; //Set TX Mode
iismod |= S3C2410_IISMOD_RXMODE;
iisfcon|= S3C2410_IISFCON_TXENABLE; //Enable TX Fifo
dstr="TX";
//setup the prescaler
audio_set_dsp_speed(audio_rate);
//iiscon has to be set last - it enables the interface
writel(iismod, iis_base + S3C2410_IISMOD);
writel(iisfcon, iis_base + S3C2410_IISFCON);
writel(iiscon, iis_base + S3C2410_IISCON);
}