Spare-SC upgrade 过程：
sc1:sc> flashupdate -f ftp://root:root@192.168.1.1/114527-13 scapp rtos
As part of this update, the system controller will automatically reboot.
RTOS will be upgraded automatically during the next boot.
ScApp will be upgraded automatically during the next boot.
Rebooting will interrupt any current operations.
This includes keyswitch changes, Solaris reboots
and all current connections.
Do you want to continue? [no] yes
Waiting for critical processes to finish. This may take a while.
Critical processes have finished.
No boards can be updated.
Rebooting the SC to automatically complete the upgrade.
Rebooting. All network client connections closed. Reestablish any needed connections.
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 47 2007/08/03 05:11
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 32MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port Intr #2
COM4 port Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x0000fffe
REF : 0x00002231
CLOCK(SELF) FREQ : 74.99 MHZ
CLOCK(OTHER) FREQ : 74.87 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
Skipping walking tests on Intr.Enable Reg
receiving heart beat from other SC
detected recent AC Power failure
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x00000099) :1.49
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 22.50 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 22.0 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 22.50 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
MAC address is MAC地址
Hostname: sc1
Address: IP地址
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 网关地址
interrupt: 100 Mbps half duplex link up
Flashupdate
Verifying network connectivity to 192.168.1.1... Passed.
Connecting to 192.168.1.1...
Transferring sgrtos.flash via FTP : 696128
Validating RTOS flash image...
Updating flashprom sectors at address 0x20000000: 11/11 = 100%
ok
Connecting to 192.168.1.1...
Transferring sgsc.flash via FTP : 6548060
Validating ScApp flash image...
Updating flashprom sectors at address 0x36000000: 100/100 = 100%
ok
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 48 2008/09/18 07:35
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 32MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port Intr #2
COM4 port Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x0000ffff
REF : 0x00002231
CLOCK(SELF) FREQ : 74.99 MHZ
CLOCK(OTHER) FREQ : 74.87 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
Skipping walking tests on Intr.Enable Reg
receiving heart beat from other SC
detected recent AC Power failure
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x00000099) :1.49
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009A) :5.1
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 22.50 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 22.0 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 22.50 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
MAC address is MAC地址
Hostname: sc1
Address: IP地址
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 网关地址
interrupt: 100 Mbps half duplex link up
Copyright 2009 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Sun Fire System Firmware
RTOS version: 48
ScApp version: 5.20.12 Build_01
SC POST diag level: min
The date is Wednesday, July 22, 2009, 10:16:40 PM EDT.
Jul 22 22:16:41 sc1 Platform.SC: Boot: ScApp 5.20.12, RTOS 48
Jul 22 22:16:47 sc1 Platform.SC: Clock Source: 75MHz
Jul 22 22:17:09 sc1 Platform.SC: Spare System Controller
Jul 22 22:17:10 sc1 Platform.SC: Starting telnet server ...
Jul 22 22:17:10 sc1 Platform.SC: SC Failover: disabled
System Controller 'sc1':
Type 0 for Platform Shell
Input:
Main-SC upgrade 过程:
sc0:SC> flashupdate -f ftp://root:root@192.168.1.1/114527-13 all rtos
As part of this update, the system controller will automatically reboot.
RTOS will be upgraded automatically during the next boot.
ScApp will be upgraded automatically during the next boot.
After this update you must reboot each active domain that was upgraded.
Rebooting will interrupt any current operations.
This includes keyswitch changes, Solaris reboots
and all current connections.
Do you want to continue? [no] yes
Waiting for critical processes to finish. This may take a while.
Critical processes have finished.
Retrieving: ftp://root:root@192.168.1.1/114527-13/sgcpu.flash
Validating ................... Done
Programming PROM /N0/SB0/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB0/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB1/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB1/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB2/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB2/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB3/FP0
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Programming PROM /N0/SB3/FP1
Erasing .................. Done
Programming .................. Done
Verifying .................. Done
Retrieving: ftp://root:root@192.168.1.1/114527-13/sgpci.flash
Validating ....... Done
Programming PROM /N0/IB6/FP0
Erasing ...... Done
Programming ...... Done
Verifying ...... Done
Programming PROM /N0/IB7/FP0
Erasing ...... Done
Programming ...... Done
Verifying ...... Done
Programming PROM /N0/IB8/FP0
Erasing ...... Done
Programming ...... Done
Verifying ...... Done
Programming PROM /N0/IB9/FP0
Erasing ...... Done
Programming ...... Done
Verifying .....Jul 22 22:27:07 sc0 Platform.SC: Stopping all services on this SC
. Done
Rebooting the SC to automatically complete the upgrade.
Rebooting. All network client connections closed. Reestablish any needed connections.
Jul 22 22:27:07 sc0 Platform.SC: All services on this SC have been stopped.
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 47 2007/08/03 05:11
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 32MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port Intr #2
COM4 port Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x0000fffe
REF : 0x0000222e
CLOCK(SELF) FREQ : 75.0 MHZ
CLOCK(OTHER) FREQ : 74.89 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
Skipping walking tests on Intr.Enable Reg
detected recent AC Power failure
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009A) :1.50
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009B) :5.4
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 24.50 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 22.0 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 26.50 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
MAC address is MAC地址
Hostname: sc0
Address: IP地址
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 网关地址
interrupt: 100 Mbps half duplex link up
Flashupdate
Verifying network connectivity to 192.168.1.1... Passed.
Connecting to 192.168.1.1...
Transferring sgrtos.flash via FTP : 696128
Validating RTOS flash image...
Updating flashprom sectors at address 0x20000000: 11/11 = 100%
ok
Connecting to 192.168.1.1...
Transferring sgsc.flash via FTP : 6548060
Validating ScApp flash image...
Updating flashprom sectors at address 0x36000000: 100/100 = 100%
ok
Software Reset...
@(#) SYSTEM CONTROLLER(SC) POST 48 2008/09/18 07:35
PSR = 0x044010e5
PCR = 0x04004000
Memory size = 32MB
SelfTest running at DiagLevel:0x20
SC Boot PROM Test
BootPROM CheckSum Test
IU Test
IU instruction set Test
Little endian access Test
FPU Test
FPU instruction set Test
SparcReferenceMMU Test
SRMMU TLB RAM Test
SRMMU TLB Read miss Test
SRMMU page probe Test
SRMMU segment probe Test
SRMMU region probe Test
SRMMU context probe Test
IIep Internal Cache Test
DCACHE RAM access Test
DCACHE TAG access Test
DCACHE Read miss Test
DCACHE Read hit Test
DCACHE Write miss Test
DCACHE Write hit Test
ICACHE RAM access Test
ICACHE TAG access Test
ICACHE miss Test
ICACHE hit Test
ICACHE TAG flush Test
PCIC Test
PCIC Probe Test
PCIC Config Register Access Test
PCI Master Abort Test
PCIC Init Test
Memory Test
Memory Address Test
MemBankAddrTest: start address = 0x00010000
RIO Ebus Test
Rio Ebus Probe Test
RIO Ethernet Test
Rio Enet Probe Test
Rio Ethernet Int Loopbacks Test
DUART(16552) InterSC Test
Loopback Test
COM3 port
COM4 port
Interrupt Test
COM3 port Intr #2
COM4 port Intr #2
System Clock Test
System Clock verify Test
Board0 Clock is selected
75MHZ Fixed Crystal is the selected Clock Source
CLK(Self) :0x0000ffff CLK(Other) : 0x0000ffff
REF : 0x0000222e
CLOCK(SELF) FREQ : 75.0 MHZ
CLOCK(OTHER) FREQ : 74.89 MHZ
SBBC PCI Controller Test
SBBC PCI Config Space probe Test
SBBC Internal Reg Access Test
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
Skipping walking tests on Intr.Enable Reg
detected recent AC Power failure
WARNING : Bit set in Sys Intr status Reg
Add: 0x38802300
Exp: 0x00000000
Obs: 0x00100000
SBBC Interrupts Test
Port1 interrupt generation Tests INTR #14
Port0 interrupt generation Tests INTR #14
SBBC Device0 Test
PS Fail Reg(SBBC Dev0) Test
SBBC Device1 Test
SRAM (SBBC Dev1) Test
Memory Address Test (Non-destructive)
SBBC Device2 Test
BId&MFG Reg (SBBC Dev2) Test
SBBC Device3 Test
FRU Prsnt Reg (SBBC Dev3) Test
SBBC Device5 Test
EPLD (SBBC Dev5) Test
TOD(M48T59) Test
TOD Init Test
TOD Functional Test
TOD NVRAM(Non-Destructive) Test
TOD Interrupts Test
I2C Register Access Test
Enable Mux Register Test
Channel Mux Register Test
Add Command Register Test
Data Register Test
Local I2C AT24C64 Test
EEPROM Device Test
performing eeprom sequential read
Local I2C PCF8591 Test
VOLT_AD Device Test
channel[00000001] Voltage(0x0000009A) :1.50
channel[00000002] Voltage(0x0000009C) :3.35
channel[00000003] Voltage(0x0000009B) :5.4
channel[00000004] Voltage(0x00000000) :0.0
Local I2C LM75 Test
TEMP0(IIep) Device Test
Temperature : 24.0 Degree(C)
Local I2C LM75 Test
TEMP1(Rio) Device Test
Temperature : 22.0 Degree(C)
Local I2C LM75 Test
TEMP2(CBH) Device Test
Temperature : 26.0 Degree(C)
Local I2C PCF8574 Test
Sc CSR Device Test
Console Bus Hub Test
CBH Register Access Test
POST Complete.
ERI Device Present
MAC address is MAC地址
Hostname: sc0
Address: IP地址
Netmask: 255.255.255.0
Attached TCP/IP interface to eri unit 0
Attaching interface lo0...done
Gateway: 网关地址
interrupt: 100 Mbps half duplex link up
Copyright 2009 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Sun Fire System Firmware
RTOS version: 48
ScApp version: 5.20.12 Build_01
SC POST diag level: min
The date is Wednesday, July 22, 2009, 10:32:28 PM EDT.
Jul 22 22:32:29 sc0 Platform.SC: Boot: ScApp 5.20.12, RTOS 48
Jul 22 22:32:35 sc0 Platform.SC: Clock Source: 75MHz
Jul 22 22:33:06 sc0 Platform.SC: Chassis is in dual partition mode.
Jul 22 22:35:06 sc0 Platform.SC: Main System Controller
Jul 22 22:35:07 sc0 Platform.SC: Added logical IP address 浮动IP地址
Jul 22 22:35:15 sc0 Platform.SC: Starting SNMP agent.
Jul 22 22:35:23 sc0 Platform.SC: Starting telnet server ...
System Controller 'sc0':
Type 0 for Platform Shell
Type 1 for domain A console
Type 2 for domain B console
Type 3 for domain C console
Type 4 for domain D console
Input:
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