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各个子模块代码如下：
D_CON.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity D_CON is
port (
MK: in STD_LOGIC;
FX :in STD_LOGIC;
CON:OUT STD_LOGIC
);
end D_CON;
architecture sc_arc of D_CON is
begin
process(FX)
begin
if FX'event and FX='1'then
CON<=MK;
end if;
end process;
end sc_arc;
test_time.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity test_time is
port (
clk_i: in STD_LOGIC;
clk_25MHz_o : out STD_LOGIC;
clk_10MHz_o : out STD_LOGIC;
CLK_5Mhz_o: out STD_LOGIC;
clk_1MHz_o : out STD_LOGIC;
clk_200KHz_o : out STD_LOGIC;
clk_1KHz_o : out STD_LOGIC;
clk_500Hz_o : out STD_LOGIC;
clk_100Hz_o : out STD_LOGIC;
clk_10Hz_o : out STD_LOGIC;
clk_2Hz_o : out STD_LOGIC;
clk_1Hz_o : out STD_LOGIC;
clk_2s_o : out STD_LOGIC
);
end test_time;
architecture test_time_arch of test_time is
signal clk_25MHz,clk_5MHz: STD_LOGIC;
signal clk_10MHz : STD_LOGIC;
signal clk_1MHz : STD_LOGIC;
signal clk_200KHz : STD_LOGIC;
signal clk_1KHz : STD_LOGIC;
signal clk_500Hz : STD_LOGIC;
signal clk_100Hz : STD_LOGIC;
signal clk_10Hz : STD_LOGIC;
signal clk_2Hz : STD_LOGIC;
signal clk_1Hz : STD_LOGIC;
signal clk_2s : STD_LOGIC;
begin
clk_25MHz_o <= clk_25MHz;
clk_5MHz_o <= clk_5MHz;
clk_10MHz_o <= clk_10MHz;
clk_1MHz_o <= clk_1MHz;
clk_200KHz_o <= clk_200KHz;
clk_1KHz_o <= clk_1KHz;
clk_500Hz_o <= clk_500Hz;
clk_100Hz_o <= clk_100Hz;
clk_2Hz_o <= clk_2Hz;
clk_1Hz_o <= clk_1Hz;
clk_2s_o <= clk_2s;
process( clk_i )
variable t : integer range 0 to 5;
begin
if ( clk_i 'event and clk_i = '1' ) then
if ( t = 1 ) then
t := 0;
clk_25MHz <= '1';
else
t := t + 1;
clk_25MHz<='0';
end if;
end if;
end process;
process( clk_i )
variable t : integer range 0 to 5;
begin
if ( clk_i 'event and clk_i = '1' ) then
if ( t = 4 ) then
t := 0;
clk_10MHz <= '1';
else
t := t + 1;
clk_10MHz<='0';
end if;
end if;
end process;
process( clk_i )
variable t : integer range 0 to 5;
begin
if ( clk_i 'event and clk_i = '1' ) then
if ( t = 9 ) then
t := 0;
clk_5MHz <= '1';
else
t := t + 1;
clk_5MHz<='0';
end if;
end if;
end process;
process( clk_i )
variable t : integer range 0 to 24;
begin
if ( clk_i 'event and clk_i = '1' ) then
if ( t = 24 ) then
t := 0;
clk_1MHz <= not clk_1MHz;
else
t := t + 1;
end if;
end if;
end process;
process( clk_1MHz )
variable t : integer range 0 to 499;
begin
if ( clk_1MHz 'event and clk_1MHz = '1' ) then
if ( t = 499 ) then
t := 0;
clk_1KHz <= not clk_1KHz;
else
t := t + 1;
end if;
end if;
end process;
process( clk_1MHz )
variable t : integer range 0 to 4;
begin
if ( clk_1MHz 'event and clk_1MHz = '1' ) then
if ( t <3 ) then
clk_200KHz <= '0';
else
clk_200KHz <= '1';
end if;
if ( t = 4 ) then
t :=0;
else
t := t + 1;
end if;
end if;
end process;
process( clk_1KHz )
variable t : integer range 0 to 4;
begin
if ( clk_1KHz 'event and clk_1KHz = '1' ) then
if ( t = 4 ) then
t := 0;
clk_100Hz <= not clk_100Hz;
else
t := t + 1;
end if;
end if;
end process;
process( clk_1KHz )
variable t : integer range 0 to 1;
begin
if ( clk_1KHz 'event and clk_1KHz = '1' ) then
if ( t = 1 ) then
clk_500Hz <= not clk_500Hz;
end if;
t := t + 1;
end if;
end process;
process( clk_100Hz )
variable t : integer range 0 to 4;
begin
if ( clk_100Hz 'event and clk_100Hz = '1' ) then
if ( t = 4 ) then
clk_10Hz <= not clk_10Hz;
t := 0;
else
t := t + 1;
end if;
end if;
end process;
process( clk_100Hz )
variable t : integer range 0 to 24;
begin
if ( clk_100Hz 'event and clk_100Hz = '1' ) then
if ( t = 24 ) then
clk_2Hz <= not clk_2Hz;
t := 0;
else
t := t + 1;
end if;
end if;
end process;
process( clk_2Hz )
variable t : integer range 0 to 1;
begin
if ( clk_2Hz 'event and clk_2Hz = '1' ) then
if ( t = 1 ) then
clk_1Hz <= not clk_1Hz;
t := 0;
else
t := t + 1;
end if;
end if;
end process;
process( clk_1Hz )
variable t : integer range 0 to 1;
begin
if ( clk_1Hz 'event and clk_1Hz = '1' ) then
if ( t = 1 ) then
clk_2s <= not clk_2s;
t := 0;
else
t := t + 1;
end if;
end if;
end process;
end test_time_arch;
lc_test.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity lc_test is
port (
clr,fs,door: in STD_LOGIC;
freq:out std_logic_vector(31 downto 0)
);
end lc_test;
architecture corn_arc of lc_test is
signal t2: std_logic_vector(31 downto 0);
signal fs_test:INTEGER range 0 to 100000000;
begin
process(fs,clr)-- N1
variable t :std_logic_vector(31 downto 0);
begin
if(clr='0') then
t:=(OTHERS=>'0');
elsif(fs'event and fs='1') then
if(door='1') then
t:=t+1;
--else
-- t:=(OTHERS=>'0');
end if;
end if;
freq<=t;
end process;
end corn_arc;
suo_frq.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity suo_frq is
port (
en: in STD_LOGIC;
data_i : in std_logic_vector(31 downto 0);
data_o:out std_logic_vector(31 downto 0)
);
end suo_frq;
architecture sc_arc of suo_frq is
begin
process(en)
begin
if en'event and en='1'then
data_o<=data_i;
end if;
end process;
end sc_arc;
需要说明的是：
连线图中：
CLK_50是一个50M信号的输入引脚，大家也可以根据自己的具体的晶振的频率编写自己的分频模块test_time，只要有1hz和25Mhz的输出信号即可。
FX是被测信号的输入管脚，输入的数字电平的高逻辑是3.3v，低逻辑是0v。
FLAG_DOWN_OUT是输出管脚，连接到CPU的外部中断管脚，一旦测好一次数据，模块自己产生一个下降沿，使CPU产生外部中断，让CPU从NX_OUT以及NS_OUT这两根32位数据总线把数据读走。这里的CPU既可以是硬核，也可以是软核（例如NIOS II）。最后由CPU计算出频率：
fre=(25000000.0/NS)*NX;//计算
上传编译成功的工程文件如下：
 |
| 文件: |
my等精度测频模块.rar |
| 大小: |
1541KB |
| 下载: |
下载 | | | 
