Chinaunix首页 | 论坛 | 博客
  • 博客访问: 1595933
  • 博文数量: 356
  • 博客积分: 8284
  • 博客等级: 中将
  • 技术积分: 4578
  • 用 户 组: 普通用户
  • 注册时间: 2009-05-15 20:25
个人简介

天行健,君子以自强不息

文章分类

全部博文(356)

文章存档

2018年(1)

2016年(4)

2015年(13)

2014年(14)

2013年(2)

2012年(25)

2011年(43)

2010年(65)

2009年(189)

分类: LINUX

2010-03-09 14:39:43

//PWM输出
//*******************************************************************************
//  MSP-FET430P440 Demo - Timer_A, PWM TA1-2 Up Mode, DCO SMCLK
//
//  Description: This program outputs two PWM signals on P1.2 and P2.0 using
//  Timer_A configured for up mode. The value in CCR0 defines the PWM period
//  and the values in CCR1 and CCR2 the PWM duty cycles. Using SMCLK as TACLK,
//  the timer period is 488us with a 75% duty cycle on P1.2 and 25% on P2.0.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz

//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//               MSP430F449
//            -----------------
//        /|\|              XIN|-
//         | |                 | 32kHz
//         --|RST          XOUT|-
//           |                 |
//           |             P1.2|--> CCR1 - 75% PWM
//           |             P2.0|--> CCR2 - 25% PWM
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21Ah
//  P1.2      TA1             P2.0      TA2
//P1.2输出的占空比CCR1/OCCR0
//P2.0输出的占空比CCR2/OCCR0,若要使它输出50%PWM,可以令CCR2=256;
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW +WDTHOLD;         // Stop WDT
  FLL_CTL0 |= XCAP14PF;            // Configure load caps
  P1DIR |= 0x04;                   // P1.2 output
  P1SEL |= 0x04;                  // P1.2 TA1 option,选择脚的第二功能
  P2DIR |= 0x01;                   // P2.0 output
  P2SEL |= 0x01;                  // P2.0 TA2 option
  CCR0 = 512-1;                    // PWM Period,PWM波的周期
// PWM Period,定时器A的捕捉比较器0计数到CCR0溢出
  CCTL1 = OUTMOD_7;          // CCR1 reset/set
  CCR1 = 384;               // CCR1 PWM duty cycle,TA1的占空比设置
  CCTL2 = OUTMOD_7;                   // CCR2 reset/set
 /*OUTMOD_7,是指 PWM output mode: 7 - PWM reset/set */
  CCR2 = 128;                        // CCR2 PWM duty cycle
  TACTL = TASSEL_2 + MC_1;           // SMCLK, up mode
//TASSEL_2是指定时器A采用SMCLK为时钟,MC_1是指采用上升模式
  _BIS_SR(LPM0_bits);                // Enter LPM0,进入低功耗模式
}

//*******************************************************************************
//  MSP-FET430P440 Demo - Timer_A, PWM TA1-2 Up Mode, 32kHz ACLK
//
//  Description: This program outputs two PWM signals on P1.2 and P2.0 using
//  Timer_A configured for up mode. The value in CCR0 defines the PWM period
//  and the values in CCR1 and CCR2 the PWM duty cycles. Using 32kHz ACLK as
//  TACLK, the timer period is 15.6ms with a 75% duty cycle on P1.2 and 25%
//  on P2.0. Normal operating mode is LPM3.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//               MSP430F449
//            -----------------
//        /|\|              XIN|-
//         | |                 | 32kHz
//         --|RST          XOUT|-
//           |                 |
//           |             P1.2|--> CCR1 - 75% PWM
//           |             P2.0|--> CCR2 - 25% PWM
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW +WDTHOLD;                  // Stop WDT
  FLL_CTL0 |= XCAP14PF;                     // Configure load caps
  P1DIR |= 0x04;                            // P1.2 output
  P1SEL |= 0x04;                            // P1.2 TA1 option
  P2DIR |= 0x01;                            // P2.0 output
  P2SEL |= 0x01;                            // P2.0 TA2 option
  CCR0 = 512-1;                             // PWM Period
  CCTL1 = OUTMOD_7;                         // CCR1 reset/set
  CCR1 = 384;                               // CCR1 PWM duty cycle
  CCTL2 = OUTMOD_7;                         // CCR2 reset/set
  CCR2 = 128;                               // CCR2 PWM duty cycle
  TACTL = TASSEL_1 + MC_1;                  // ACLK, up mode
  _BIS_SR(LPM3_bits);                       // Enter LPM3
}

看门狗定时器
//******************************************************************************
//  MSP-FET430P440 Demo - WDT, Toggle P5.1, Interval Overflow ISR, 32kHz ACLK
//
//  Description: Toggle P5.2 using WDT configured for Interval Timer mode.
//  Interrupt toggles LED every 1000ms based on 32kHz ACLK WDT clock source.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//                 MSP430F449
//             -----------------
//         /|\|              XIN|-
//          | |                 | 32kHz
//          --|RST          XOUT|-
//            |                 |
//            |             P5.2|-->LED
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//*****************************************************************************
#include
void main(void)
{
  WDTCTL = WDT_ADLY_1000;                    // WDT 1000ms, ACLK, interval timer
  IE1 |= WDTIE;                             // Enable WDT interrupt
  FLL_CTL0 |= XCAP14PF;                     // Configure load caps
  P5DIR |= 0x04;                            // Set P5.2 to output direction
  _BIS_SR(LPM3_bits + GIE);                 // Enter LPM3 w/interrupt
}
// Watchdog Timer interrupt service routine
#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer(void)
{
  P5OUT ^= 0x04;      // Toggle P5.2 using exclusive-OR,使P5.2每隔1s翻转一次
}
 

 
AD+数码管显示
 
弄了半天,终于把AD的程序弄好了,虽然数码管闪烁的比较厉害,但总算结果出来了,代码如下:
 
//******************************************************************************
//  MSP-FET430P440 Demo - ADC12, Using the Internal Reference
//
//  This example shows how to use the internal reference of the ADC12.
//  It uses the internal 2.5V reference and performs a single conversion
//  on channel A0. The conversion results are stored in ADC12MEM0. Test by
//  applying a voltage to channel A0
//  ACLK = n/a, MCLK = SMCLK = default DCO, ADC12CLK = ADC12OSC
//
//
//                MSP430F449
//             ---------------
//            |               |
//     Vin -->|P6.0/A0        |
//            |               |
//
//
//  AD转换的 结果保存在ADC12MEM0里面
//******************************************************************************
#include 
#define   SHUMA_PORT_DIR  P2DIR//数码管数据口
#define   SHUMA_PORT_OUT  P2OUT
#define   SHUMA_1_LOW     P3OUT&=~BIT4//开数码管的第一位
#define   SHUMA_1_HIGH    P3OUT|=BIT4//灭第一位数码管
#define   SHUMA_2_LOW     P3OUT&=~BIT5//开数码管的第二位
#define   SHUMA_2_HIGH    P3OUT|=BIT5//灭数码管的第二位
#define   SHUMA_3_LOW     P3OUT&=~BIT6//开数码管的第三位
#define   SHUMA_3_HIGH    P3OUT|=BIT6//灭数码管的第三位
#define   SHUMA_4_LOW     P3OUT&=~BIT7//开数码管的第四位
#define   SHUMA_4_HIGH    P3OUT|=BIT7//灭数码管的第四位
//void int_clk();//时钟初始化子程序声明
void delay_352us(unsigned int i);//352us延时程序声明
const unsigned char tabl1[11]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90,0x00};
                             // ;0  ,1   ,2   ,3  , 4,   5,   6    ,7   ,8  ,9 ,灭
//IO口初始化子程序
void int_shuma_io()
{
  SHUMA_PORT_DIR|=0XFF;//set P5 is out  设置控制数码管数据口的IO口为输出模式
  P3DIR|=BIT7+BIT4+BIT5+BIT6;
  P3DIR|=BIT3;//P3.0控制74HC573的OE,把这个口设置为输出
  P3OUT&=~BIT3;//使能74573,使得74573的输出随输入变化
}
//******************************************************
//352微秒延时程序
void delay_352us(unsigned int i)//352us延时程序,延时时间的计算在前面已经讲过
{
  unsigned char j;
 
  while(i--)
  {
   for(j=0;j<255;j++)
   { 
    _NOP();
    _NOP();
    _NOP();
    _NOP();  
    }
  }

void display(int z)
{
   //以下是数码管的动态扫描程序
   unsigned char DISPLAY1,DISPLAY2,DISPLAY3,DISPLAY4;
   DISPLAY1=z/1000;
   DISPLAY2=z%1000/100;
   DISPLAY3=z%100/10;
   DISPLAY4=z%10;
   SHUMA_PORT_OUT=tabl1[DISPLAY1]+0x80;//求取BCD码对应的数码管段码,并送到控制数码管的数据扣
   SHUMA_1_LOW;//开第一位数码管
   delay_352us(2);//简单延时
   SHUMA_1_HIGH;//灭第一位数码管
   SHUMA_PORT_OUT=tabl1[DISPLAY2];//送数码管第二位显示的段码
   SHUMA_2_LOW;//开显示第二位数码管
   delay_352us(2);//延时
   SHUMA_2_HIGH;//灭第二位数码管,接下去重复1二
   SHUMA_PORT_OUT=tabl1[DISPLAY3];
   SHUMA_3_LOW;
   delay_352us(2);
   SHUMA_3_HIGH;
   SHUMA_PORT_OUT=tabl1[DISPLAY4];
   SHUMA_4_LOW;
   delay_352us(2);
   SHUMA_4_HIGH;
}
//*************************************
float value;
void main(void)
{
  unsigned int i;
  WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer
  int_shuma_io();//初始化数码管控制口
  P6SEL |= 0x01;                            // Enable A/D channel A0
  ADC12CTL0 = ADC12ON+SHT0_2+REFON+REF2_5V; // Turn on and set up ADC12
  ADC12CTL1 = SHP;                          // Use sampling timer
  ADC12MCTL0 = SREF_1;                      // Vr+=Vref+
  for ( i=0; i<0x3600; i++)                 // Delay for reference start-up
  {
  }
  ADC12CTL0 |= ENC;                         // Enable conversions
  while (1)
  {
    ADC12CTL0 |= ADC12SC;                   // Start conversion
    if((ADC12IFG & BIT0)!=0)
    {
      value=(float)(ADC12MEM0);
      value=(int)(value/4096*2.5*1000);
      //while(1)
      {
       display(value);
      }
    }
   // _NOP();                                 // SET BREAKPOINT HERE
  }
}
注:模拟电压有P6.0输入,单片机采用的是内部2.5v参考电压。测量范围为0-2.5v,超过2.5v就测不出来。
虽然msp430f449自称是12位的AD转换,但误差却相当大,为0.2v左右!

 
低功耗模式3(LPM3)
 
//******************************************************************************
//  MSP-FET430P440 Demo - FLL+, LPM3 Using Basic Timer ISR, 32kHz ACLK
//
//  Description: System runs normally in LPM3 with basic timer clocked by
//  32kHz ACLK. At a 2 second interval the basic timer ISR will wake the
//  system and flash the LED on P5.2 inside of the Mainloop(主循环).
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//
//           MSP430F449
//         ---------------
//     /|\|            XIN|-
//      | |               | 32kHz
//      --|RST        XOUT|-
//        |               |
//        |           P5.2|-->LED
//
//IAR Embedded Workbench Version: 3.21A
//系统的常态是低功耗模式3,每隔2秒钟由ACLK提供的基本时钟来唤醒cpu使led闪烁
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  FLL_CTL0 |= XCAP14PF;                     // Configure load caps
  IE2 |= BTIE;                              // Enable basic timer interrupt
  BTCTL = BTDIV+BTIP2+BTIP1+BTIP0;          // 2s Interrupt,设置中断的时间
  P1DIR = 0xFF;                             // All P1.x outputs
  P1OUT = 0;                                // All P1.x reset
  P2DIR = 0xFF;                             // All P2.x outputs
  P2OUT = 0;                                // All P2.x reset
  P3DIR = 0xFF;                             // All P3.x outputs
  P3OUT = 0;                                // All P3.x reset
  P4DIR = 0xFF;                             // All P4.x outputs
  P4OUT = 0;                                // All P4.x reset
  P5DIR = 0xFF;                             // All P5.x outputs
  P5OUT = 0;                                // All P5.x reset
  P6DIR = 0xFF;                             // All P6.x outputs
  P6OUT = 0;                                // All P6.x reset
  while(1)
  {
    int i;
    _BIS_SR(LPM3_bits + GIE);               // 进入低功耗模式三,使能全局中断
    //过了两秒后,进入中断函数
    P5OUT |= 0x04;                          // Set P5.2 LED on
    for (i = 5000; i>0; i--);    //一段很短时间的延时,为的是为了让人眼看出led亮了
    P5OUT &= ~0x04;                         // Clear P5.2 LED off
  }
}
// Basic Timer interrupt service routine
#pragma vector=BASICTIMER_VECTOR
__interrupt void basic_timer(void)
{
    _BIC_SR_IRQ(LPM3_bits);          // 清除低功耗标志位,唤醒系统,使cpu运转
}

定时器A
//******************************************************************************
//  MSP-FET430P440 Demo - Timer_A, Toggle P5.1, CCR0 Up Mode ISR, 32kHz ACLK
//
//  Description: Toggle P5.1 using software and the TA_0 ISR. Timer_A is
//  configured for up mode, thus the the timer overflows when TAR counts
//  to CCR0. In this example, CCR0 is loaded with 1000-1. LED toggles every
//  30.5ms.
//计算方法如下:1/32768*(1000-1)*1000=30.5ms
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//           MSP430F449
//         ---------------
//     /|\|            XIN|-
//      | |               | 32kHz
//      --|RST        XOUT|-
//        |               |
//        |           P5.1|-->LED
//
//定时器会溢出产生中断当TAR计数到CCR0
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  FLL_CTL0 |= XCAP14PF;                     // Configure load caps
  P5DIR |= 0x02;                            // Set P5.1 to output direction
  CCTL0 = CCIE;                             // 使能CCR0中断
  CCR0 = 1000-1;
  TACTL = TASSEL_1 + MC_1; //定时器A的时钟源选择ACLK,上升模式,一直计数到CCR0
  _BIS_SR(LPM3_bits + GIE); // 进入低功耗模式三,开全局总中断
}
// Timer A0 interrupt service routine
#pragma vector=TIMERA0_VECTOR
__interrupt void Timer_A (void)
{
    P5OUT ^= 0x02;          //计算方法如下:1/32768*(1000-1)*1000=30.5ms
}

 
/*本程序是利用定时器A模块中的CCR0捕获/比较寄存器的值与定时器A的值
进行比较当TA大于等于CCR0时,TA被清零重新由0开始计数。在此同时,
CCR0产生中断*/

//注:__interrupt void Timer_A(void)前面的是两个下划线
#include
void main(void)
{
    WDTCTL=WDTPW+WDTHOLD;//关闭看门狗
    P1DIR|=0X01;
    CCTL0=CCIE;     //CCR0(捕捉比较寄存器)开中断允许
    CCR0=1000-1;   
    TACTL=TASSEL_1+MC_1;//以ACLK作为定时器A的时钟源,采用增计数模式
    _BIS_SR(LPM3_bits+GIE);//进入LPM3模式,开总中断允许
}
#pragma vector=TIMERA0_VECTOR
__interrupt void Timer_A(void)
//__interrupt void Timer_A(void)
{
    P1OUT^=0X01;  
}

 
Timer  B
//******************************************************************************
//  MSP-FET430P440 Demo - Timer_B, Toggle P5.1, CCR0 Up Mode ISR, DCO SMCLK
//
//  Description: Toggle P5.1 using software and TB_0 ISR. Timer_B is
//  configured for up mode, thus the timer overflows when TBR counts to
//  CCR0. In this example, CCR0 is loaded with 20000.
//  ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO
//
//           MSP430F449
//         ---------------
//     /|\|            XIN|-
//      | |               |
//      --|RST        XOUT|-
//        |               |
//        |           P5.1|-->LED
//
//当TBR计数到CCR0时,定时器B就会溢出
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P5DIR |= 0x02;                            // Set P5.1 to output direction
  TBCCTL0 = CCIE;                           // TBCCR0 interrupt enabled
  TBCCR0 = 20000;        //设置timerB的初值为20000,超过后就会溢出,触发中断
  TBCTL = TBSSEL_2 + MC_1;                  // SMCLK, up mode
  _BIS_SR(LPM0_bits + GIE);                 // Enter LPM0 w/ interrupt
}
// Timer B0 interrupt service routine
#pragma vector=TIMERB0_VECTOR
__interrupt void Timer_B (void)
{
  P5OUT ^= 0x02;                            // Toggle P5.1 using exclusive-OR
}

 
//******************************************************************************
//  MSP-FET430P440 Demo - Timer_B, Toggle P5.1, CCR0 Up Mode ISR, 32kHz ACLK
//
//  Description: Toggle P5.1 using software and the TB_0 ISR. Timer_B is
//  configured for up mode, thus the the timer overflows when TBR counts
//  to CCR0. In this example, CCR0 is loaded with 32768. LED toggles every
// 1s.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//           MSP430F449
//         ---------------
//     /|\|            XIN|-
//      | |               | 32kHz
//      --|RST        XOUT|-
//        |               |
//        |           P5.1|-->LED
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  FLL_CTL0 |= XCAP14PF;                     // Configure load caps
  P5DIR |= 0x02;                            // Set P5.1 to output direction
  TBCCTL0 = CCIE;                           // TRCCR0 interrupt enabled
  //定时器B捕捉比较控制器0使能
  TBCCR0 = 32768;//设定定时器B捕捉比较控制器0的初值
  TBCTL = TBSSEL_1 + MC_1;                  // ACLK, up mode
//以ACLK作为定时器B的时钟,采用上升模式
  _BIS_SR(LPM3_bits + GIE);                 // Enter LPM3 w/ interrupt
}
// Timer B0 interrupt service routine
#pragma vector=TIMERB0_VECTOR
__interrupt void Timer_B (void)
{
    P5OUT ^= 0x02;                          // Toggle P5.1 using exclusive-OR
}

6路PWM波同时输出
 
  //*******************************************************************************
//  MSP-FET430P440 Demo - Timer_B, PWM TB1-6 Up Mode, DCO SMCLK
//
//  Description: This program outputs six PWM signals on P2.2,3 and P3.4-7
//  using Timer_B configured for up mode. The value in CCR0 defines the PWM
//  period
and the values in CCR1-6 the PWM duty cycles. Using SMCLK as TBCLK,
//  the timer period is ~488us.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//               MSP430F449
//            -----------------
//        /|\|              XIN|-
//         | |                 | 32kHz
//         --|RST          XOUT|-
//           |                 |
//           |         P2.2/TB1|--> CCR1 - 75% PWM
//           |         P2.3/TB2|--> CCR2 - 25% PWM
//           |         P3.4/TB3|--> CCR3 - 12.5% PWM
//           |         P3.5/TB4|--> CCR4 - 6.25% PWM
//           |         P3.6/TB5|--> CCR5 - 3.125% PWM
//           |         P3.7/TB6|--> CCR6 - 1.5625% PWM
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  FLL_CTL0 |= XCAP18PF;                     // Configure load caps
  P2DIR |= 0x0c;     // P2.2 - P2.3 output,CCR1,CCR2
  P2SEL |= 0x0c;     // P2.3 - P2.3 选择第二功能
  P3DIR |= 0xF0;     // P3.4 - P3.7 output,CCR3,CCR4,CCR5,CCR6
  P3SEL |= 0xF0;                            // P3.4 - P3.7 选择第二功能
  TBCCR0 = 512-1;                           // PWM Period
  //设定定时器B捕获比较器0的初值,决定PWM波的频率
  TBCCTL1 = OUTMOD_7;                       // CCR1 重置
  TBCCR1 = 384;                             // CCR1 PWM 占空比
  TBCCTL2 = OUTMOD_7;//CCR2
  TBCCR2 = 128;
  TBCCTL3 = OUTMOD_7;//CCR3
  TBCCR3 = 64;
  TBCCTL4 = OUTMOD_7;//CCR4
  TBCCR4 = 32;
  TBCCTL5 = OUTMOD_7;//CCR5
  TBCCR5 = 16;
  TBCCTL6 = OUTMOD_7;//CCR6
  TBCCR6 = 8;
  TBCTL = TBSSEL_2 + MC_1;                  // SMCLK, up mode
  //以SMCLK作为定时器B的时钟,采用上升方式

  _BIS_SR(CPUOFF);                          // Enter LPM0
}
 

 
//******************************************************************************
//  MSP-FET430P440 Demo - Timer_B, Toggle P5.1, Overflow ISR, 32kHz ACLK
//
//  Description: Toggle P5.1 using software and the Timer_B overflow ISR.
//  In this example an ISR triggers when TB overflows. Inside the ISR P5.1
//  is toggled. Toggle rate is exactly 0.5Hz.
//  Proper use of the TBIV interrupt vector generator is demonstrated.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//           MSP430F449
//         ---------------
//     /|\|            XIN|-
//      | |               | 32kHz
//      --|RST        XOUT|-
//        |               |
//        |           P5.1|-->LED
//
//定时器A直接计数溢出产生中断,然后中断处理
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;         // Stop WDT
  FLL_CTL0 |= XCAP14PF;            // Configure load caps
  P5DIR |= 0x02;                   // Set P5.1 to output direction
  TBCTL = TBSSEL_1 + MC_2 + TBIE;  // 以ACLK作为定时器B的时钟源,采用连续上升模式,定时器B中断使能
  _BIS_SR(LPM3_bits + GIE);    //进入低功耗模式三,开全局中断
}
// Timer_B7 Interrupt Vector (TBIV) handler
#pragma vector=TIMERB1_VECTOR
__interrupt void Timer_B(void)
{
 switch( TBIV )           //应用switch语句处理多中断源的向量
 {
   case  2: break;                          // CCR1捕获比较寄存器的入口,不用
   case  4: break;                          // CCR2捕获比较寄存器的入口,不用
   case 14: P5OUT ^= 0x02;                  // 定时器B计满时将产生计数溢出中断
            break;
  }

}

 
 
//*******************************************************************************
//  MSP-FET430P140 Demo - Timer_B, PWM TB1-6 Up Mode, 32kHz ACLK
//
//  Description; This program outptus six PWM signals on P2.2,3 and P3.4-7
//  using Timer_B configured for up mode. The value in CCR0 defines the PWM
//  period and the values in CCR1-6 the PWM duty cycles. Using 32kHz ACLK
//  as TBCLK, the timer period is 15.6ms. Normal operating mode is LPM3.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//               MSP430F449
//            -----------------
//        /|\|              XIN|-
//         | |                 | 32kHz
//         --|RST          XOUT|-
//           |                 |
//           |         P2.2/TB1|--> CCR1 - 75% PWM
//           |         P2.3/TB2|--> CCR2 - 25% PWM
//           |         P3.4/TB3|--> CCR3 - 12.5% PWM
//           |         P3.5/TB4|--> CCR4 - 6.25% PWM
//           |         P3.6/TB5|--> CCR5 - 3.125% PWM
//           |         P3.7/TB6|--> CCR6 - 1.5625% PWM

//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include
void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  FLL_CTL0 |= XCAP18PF;                     // Configure load caps
  P2DIR |= 0x0c;                            // P2.2 - P2.3 output
  P2SEL |= 0x0c;                            // P2.3 - P2.3 TBx options
  P3DIR |= 0xF0;                            // P3.4 - P3.7 output
  P3SEL |= 0xF0;                            // P3.4 - P3.7 TBx options
  TBCCR0 = 512-1;                           // PWM Period
  TBCCTL1 = OUTMOD_7;                       // CCR1 reset/set
  TBCCR1 = 384;                             // CCR1 PWM duty cycle
  TBCCTL2 = OUTMOD_7;
  TBCCR2 = 128;
  TBCCTL3 = OUTMOD_7;
  TBCCR3 = 64;
  TBCCTL4 = OUTMOD_7;
  TBCCR4 = 32;
  TBCCTL5 = OUTMOD_7;
  TBCCR5 = 16;
  TBCCTL6 = OUTMOD_7;
  TBCCR6 = 8;
  TBCTL = TBSSEL_1 + MC_1;                  // ACLK, up mode
 //以ACLK作为定时器B的时钟,采用上升模式,这是此例和上面的那个唯一不同之处
  _BIS_SR(LPM3_bits);                       // Enter LPM3
}

时钟信号输出
//*****************************************************************************
//  MSP-FET430P430 Demo - FLL+, Output 32kHz Xtal + HF Xtal + Internal DCO
//
//  Description: This program demonstrates using an external 32kHz crystal to
//  supply ACLK, and using a high speed crystal or resonator(谐振器)to supply SMCLK.
//  MLCK for the CPU is supplied by the internal DCO. The 32kHz crystal
//  connects between pins Xin and Xout. The high frequency crystal or
//  resonator connects between pins XT2IN and XT2OUT. The DCO clock is
//  generated internally and calibrated(校准) from the 32kHz crystal. ACLK is
//  brought out on pin P1.5, SMCLK is brought out on P1.4, and MCLK is
//  brought out on pin P1.1.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
//  //* An external watch crystal between XIN & XOUT is required for ACLK *// 
//
//  NOTE: External matching capacitors must be added for the high
//       speed crystal or resonator as required.
//
//                 MSP430F449
//             -----------------
//        /|\ |             XIN|-
//         |  |                 | 32kHz
//         ---|RST         XOUT|-
//            |                 |
//            |                 |
//            |           XT2IN|-
//            |                 | HF XTAL or Resonator (add capacitors)
//            |          XT2OUT|-
//            |                 |
//            |          P1.5|--> ACLK = 32kHz Crystal Out,32.77KHZ
//            |                 |
//            |          P1.4|--> SMCLK = High Freq Xtal or Resonator Out,8M
//            |                 |
//            |          P1.1|--> MCLK = Default DCO Frequency,1M
//            |                 |
//            |                 |
//ACLK(辅助系统时钟),sourced from a 32768HZ watch crystal or a high frequence crystall
//MCLK,主系统时钟,被CPU使用的时钟
//SMCLK,被外设使用的时钟
//ACLK/n,the buffered output of ACLK,ACLK/2,ACLK/4,ACLK/8
//*****************************************************************************
#include 
void main(void)
{
  unsigned int i;
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  FLL_CTL0 |= XCAP18PF;                     // Set load capacitance
  FLL_CTL1 &= ~XT2OFF;                      // Turn on XT2
  // Loop until 32kHz crystal stabilizes(稳定)
  do
  {
    IFG1 &= ~OFIFG;                         // Clear oscillator fault flag
    for (i = 50000; i; i--);                // Delay
  }
  while (IFG1 & OFIFG);                     // Test osc fault flag
  FLL_CTL1 = SELS;                          // Select SMCLK source as XT2CLK
  P1DIR = 0x32;                             // Set P1.1,4,5 as outputs
  P1SEL = 0x32;                             // Select P1.1,4,5 as clocks
  while(1);                                 // Loop in place
}

MSP430的端口有P1、P2、P3、P4、P5、P6、S和COM(型号不同,包含的端口也不仅相同,如MSP430X11X系列只有P1,P2端口,而MSP430X4XX系列则包含全部上述端口),它们都可以直接用于输入/输出。MSP430系统中没有专门的输入/输出指令,输入/输出操作通过传送指令来实现。端口P1`P6的每一位都可以独立用于输入/输出,即具有位寻址功能。常见的键盘接口可以直接用端口进行模拟,用查询或者中断方式控制。由于MSP430的端口只有数据口,没有状态口或控制口,在实际应用中,如在查询式输入/输出传送时,可以用端口的某一位或者几位来传送状态信息,通过查询对应位的状态来确定外设是否处于“准备好”状态。
       端口的功能。(1)P1,P2端口: I/O,中断功能,其他片内外设功能如定时器、比较器;(2)P3,P4P5P6端口:I/O,其他片内外设功能如SPI、UART模式,A/D转换等;(3)S,COM端口:I/O,驱动液晶。
       MSP430各端口具有丰富的控制寄存器供用户实现相应的操作。其中P1,P2具有7个寄存器,P3~P6具有4个寄存器。通过设置寄存器我们可以实现:(1)每个I/O位独立编程;(2)任意组合输入,输出和中断;(3)P1,P2所有8个位全部可以用作外部中断处理;(4)可以使用所以指令对寄存器操作;(5)可以按字节输入、输出,也可按位进行操作。
       端口P1,P2的功能可以通过它们的7个控制寄存器来实现。这里,Px代表P1或P2。
(1)PxDIR:输入/输出方向寄存器。  8位相互独立,可以分别定义8个引脚的输入/输出方向。8位再PUC后都被复位。使用输入/输出功能时,应该先定义端口的方向 。作为输入时只能读,作为输出时,可读可写。0:输入模式;1:输出模式。如:P1DIR|=BIT4;   //P1.4输出 ,P2DIR=0XF0;   //高4位输出,低4位输入。
(2)PXIN:输入寄存器,为只读寄存器。用户不能对它进行写入,只能通过读取其寄存器的内容来知道I/O口的输入信号。所以其引脚的方向要选为输入。如再键盘键盘扫描程序中经常要读取行线或者列线的端口寄存器值来判断案件情况。例如:unsigned char key;
P1DIR&=~BIT4;   //P1.4输入
……
key=P1IN&0X10;   //输出端口P1.4的值
……
(3)PXOUT:输出寄存器。该寄存器为I/O端口的输出缓冲寄存器,再读取时输出缓存的内容与引脚方向定义无关。改变方向寄存器的内容,输出缓存的内容不受影响。如:PIOUT|=0X01;   //P1.0输出1  , PIOUT&=~0X01;   //P1.0输出0 。
(4)PXIFG:中断标志寄存器。他的8个标志位标志相应引脚是否有中断请求有待处理。0:无中断请求,  1:有中断请求。其中断标志分别为PXIFG.0~PXIFG.7。应该注意的是:PXIFG.0~PXIFG.7共用一个中断向量,为多源中断。当任一事件引起的中断进行处理时,PXIFG.0~PXIFG.7不会自动复位,必须由软件来判断是对哪一个事件,并将相应的标志复位。另外,外部中断事件的时间必须保持不低于1.5倍的MCLK时间,以保证中断请求被接受,且使相应中断标志位置位。
(5)PXIES:中断触发沿选择寄存器。如果允许PX口的某个引脚中断,还需定义该引脚的中断触发方式。0:上升沿触发使相应标志置位,1:下降沿触发相应标志置位。如:MOV.B  #07H, &P1IES  ;p1低3位下降沿触发中断。
(6)PXIE:中断使能寄存器。PX口的每一个引脚都有一位用以控制该引脚是否允许中断。0:禁止中断 ,1:允许中断。MOV.B  #0E0H, &P2IE  ;P2高3位允许中断。
(7)PXSEL:功能选择寄存器。P1,P2两端口还具有其他片内外设功能,将这些功能与芯片外的联系通过复用P1,P2引脚的方式来实现。PXSEL用来选择引脚的I/O端口功能与外围模块功能。0:选择引脚为I/O端口,1:选择引脚为外围模块功能。如:P1SEL|=0X10;  //P1.4为外围模块功能。
       端口P3、P4、P5、P6没有中断能力,其余功能同PI,P2。除掉端口P1,P2与中断相关的3个寄存器,端口P3,P4,P5,P6的4个寄存器(用法同P1,P2)分别为PXDIR,PXIN,PXOUT,PXSEL可供用户使用。
      端口COM和S,他们实现与液晶片的直接接口。COM为液晶片的公共端,S为液晶片的段码端。液晶片输出端也可经软件配置为数字输出端口。
阅读(3116) | 评论(0) | 转发(0) |
给主人留下些什么吧!~~