按键检测（修改别人程序并测试成功）

module key_jiance_ceshi(
clk,
rst_n,
sw1,
sw2,
sw3,
//output
led_d3,
led_d4,
led_d5
);

input clk;
input rst_n;
input sw1,sw2,sw3; //Active low
output led_d3;
output led_d4;
output led_d5;

// ---------------------------------------------------------------------------
// 通过降采样对sw1~sw3的输入做低通滤波，将其高频分量滤除,得到low_sw值
// ---------------------------------------------------------------------------
reg [19:0] cnt;
always @ (posedge clk or negedge rst_n)
 if (!rst_n)
  cnt <= 20'd0;
 else
  cnt <= cnt + 1'b1;

reg [2:0] low_sw;
always @(posedge clk or negedge rst_n)
 if (!rst_n)
  low_sw <= 3'b111;
 else if (cnt == 20'd100_0000) //每隔20MS检测一次按键
  low_sw <= {sw3,sw2,sw1};
  
reg [2:0] low_sw_r; //将low_sw信号锁存一个时钟周期，延时不是真的“锁存”

always @ ( posedge clk or negedge rst_n )
 if (!rst_n)
  low_sw_r <= 3'b111;
 else
  low_sw_r <= low_sw;

wire [2:0] led_ctrl = low_sw_r[2:0] & ( ~low_sw[2:0]);

reg d1,d2,d3;

always @ (posedge clk or negedge rst_n)
 if (!rst_n)
  begin
  d1 <= 1'b0;
  d2 <= 1'b0;
  d3 <= 1'b0;
  end
 else
  begin
  if ( led_ctrl[0] ) d1 <= ~d1;
  if ( led_ctrl[1] ) d2 <= ~d2;
  if ( led_ctrl[2] ) d3 <= ~d3;
  end
assign led_d3=d1;

文件:	key_jiance_ceshi.rar
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assign led_d4=d2;
assign led_d5=d3;

endmodule