/*
blue 00_11_11
yellow 11_00_11
blue 11_11_00
0 bu liang
1 liang
*/
module traffic(led_l,led_r,clk,seg_reg1,seg_reg2,inter_key);
input clk,inter_key;
output [6:0] seg_reg1,seg_reg2;
output [5:0] led_l,led_r;
reg [6:0] dispdat1,dispdat2,seg_reg1,seg_reg2;
reg [25:0] count;
reg [1:0] led_yellow_l;
reg [1:0] led_blue_l;
reg [1:0] led_red_l;
reg [5:0] led_reg_l;
reg [1:0] led_yellow_r;
reg [1:0] led_blue_r;
reg [1:0] led_red_r;
reg [5:0] led_reg_r;
reg [3:0] flag_shuma0,flag_shuma1;
reg [5:0] flag_led_l,flag_led_r;
reg flag;
reg [1:0] flag_rgy_status;
reg sec;
reg [1:0] rgy_status;
reg [7:0] rgy_time;
initial
begin
flag_rgy_status=2'd0;
rgy_time=8'h30; //status 0 time
led_reg_l=6'b000000;
led_reg_r=6'b000000;
flag=1'b0;
end
////////////////////////fen ping chan sheng 2HZ shi zhong/////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
count=count+1;
if(count==26'd1000_0000) //should be 2500_0000
begin
count=0;
sec=~sec; //2 HZ
end
end
///////////////////////////////status 0/////////////////////////////////////////////////
always @(posedge sec)
begin
if(rgy_status==2'd0)
begin
if(rgy_time==8'h0)
begin
rgy_status=2'd1;
rgy_time=8'h21; //status 1 time short time
//led_red=led_reg[3:0];
end
else
begin
led_reg_l=6'b110000; //blue
led_reg_r=6'b000011; //red
rgy_time=rgy_time-1'b1;
if(rgy_time[3:0]>9)
rgy_time[3:0]=9;
end
end
////////////////////////////////////status 1/////////////////////////////////////////////
if(rgy_status==2'd1)
begin
if(rgy_time==8'h0)
begin
rgy_status=2'd2;
rgy_time=8'h31; //status 2 time
end
else
begin
led_reg_l=6'b001100; //yellow
led_reg_r=6'b000011; //red
rgy_time=rgy_time-1;
if(rgy_time[3:0]>9)
rgy_time[3:0]=9;
end
end
////////////////////////////////////status 2//////////////////////////////////////
if(rgy_status==2'd2)
begin
if(rgy_time==8'h0)
begin
rgy_status=2'd3;
rgy_time=8'h21; // short time
end
else
begin
led_reg_l=6'b000011; //red
led_reg_r=6'b110000; //blue
rgy_time=rgy_time-1;
if(rgy_time[3:0]>9)
rgy_time[3:0]=9;
end
end
//////////////////////////////////zhuang tai 3///////////////////////////////////////////
if(rgy_status==2'd3)
begin
if(rgy_time==8'h0)
begin
rgy_status=2'd0; //return to status 0
rgy_time=8'h30;
end
else
begin
led_reg_l=6'b000011; //red
led_reg_r=6'b001100; //yellow
rgy_time=rgy_time-1;
if(rgy_time[3:0]>9)
rgy_time[3:0]=9;
end
end
end
////////////////////////////xian shi ji shi///////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
/////////////////////super time(red-------red)/////////////////////////////////////////////
always
begin
if(inter_key==1)
begin
flag_shuma0=rgy_time[3:0];
flag_shuma1=rgy_time[7:4];
flag_led_l=led_reg_l;
flag_led_r=led_reg_r;
end
else
begin
flag_shuma0=4'h10;
flag_shuma1=4'h10;
flag_led_l=6'b000011;
flag_led_r=6'b000011;
flag=1'b1;
end
end
/////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////cun zai wen ti(dai wan shan)///////////////////////////
always @(flag)
begin
if(flag==1'b1)
begin
flag=1'b0;
//rgy_status=flag_rgy_status;
//rgy_time=8'h30; //status 0 time
//led_reg_l=6'b000000;
//led_reg_r=6'b000000;
end
end
///////////////////////////cun zai wen ti///////////////////////////////////////
always
begin
dispdat1=flag_shuma0;
dispdat2=flag_shuma1;
end
always @(dispdat1)
begin
case(dispdat1)
4'h0:seg_reg1=7'b1000000;//0
4'h1:seg_reg1=7'b1111001;//1
4'h2:seg_reg1=7'b0100100;//2
4'h3:seg_reg1=7'b0110000;//3
4'h4:seg_reg1=7'b0011001;//4
4'h5:seg_reg1=7'b0010010;//5
4'h6:seg_reg1=7'b0000010;//6
4'h7:seg_reg1=7'b1111000;//7
4'h8:seg_reg1=7'b0000000;//8
4'h9:seg_reg1=7'b0010000;//9
4'h10:seg_reg1=7'b1111111;//not display
endcase
end
//////////////////////////////////////////////////////////////////////////////////////////
always @(dispdat2)
begin
case(dispdat2)
4'h0:seg_reg2=7'b1000000;//0
4'h1:seg_reg2=7'b1111001;//1
4'h2:seg_reg2=7'b0100100;//2
4'h3:seg_reg2=7'b0110000;//3
4'h4:seg_reg2=7'b0011001;//4
4'h5:seg_reg2=7'b0010010;//5
4'h6:seg_reg2=7'b0000010;//6
4'h7:seg_reg2=7'b1111000;//7
4'h8:seg_reg2=7'b0000000;//8
4'h9:seg_reg2=7'b0010000;//9
4'h10:seg_reg2=7'b1111111;//not display
endcase
end
assign led_l=flag_led_l;
assign led_r=flag_led_r;
endmodule
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