module timer_led(clk,seg_reg);
input clk;
output [6:0] seg_reg;
reg [3:0] disp_dat;
reg [27:0] count;
reg [6:0] seg_reg;
///////////////////count time//////
always @(posedge clk)
begin
count=count+1;
if(disp_dat>14)
count=28'b0000000000000000000000000000;
end
//////////////////////////
always
begin
disp_dat=count[27:24]; //xian shi shu zhi
if(disp_dat>14)
begin
disp_dat=4'b0000;
end
end
/////////////////////duan xuan/////////////////////////////
always @(disp_dat)
begin
case(disp_dat)
4'h0:seg_reg=7'b1000000;//0
4'h1:seg_reg=7'b1111001;//1
4'h2:seg_reg=7'b0100100;//2
4'h3:seg_reg=7'b0110000;//3
4'h4:seg_reg=7'b0011001;//4
4'h5:seg_reg=7'b0010010;//5
4'h6:seg_reg=7'b0000010;//6
4'h7:seg_reg=7'b1111000;//7
4'h8:seg_reg=7'b0000000;//8
4'h9:seg_reg=7'b0010000;//9
4'ha:seg_reg=7'b0001000;//a
4'hb:seg_reg=7'b0000011;//b
4'hc:seg_reg=7'b1000110;//c
4'hd:seg_reg=7'b0100001;//d
4'he:seg_reg=7'b0000110;//e
endcase
end
endmodule
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