module led_water(clk,led);
input clk;
output [7:0] led;
reg [7:0] led;
reg [22:0] buffer;
initial
led=9'b111111111;
always @(posedge clk)
begin
buffer=buffer+1;
if(buffer==23'd5529630)
begin
led=led<<1;
if(led==9'b000000000)
led=9'b111111111;
end
end
endmodule
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