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2009-09-08 02:55:37

二、下载源代码
U-BOOT-1.3.2:
ELDK:
(本来是用2.95的arm-elf-gcc来编译的,但是出现的问题太多,软浮点,-MQ选项不支持等等,网上说的我全部都遇到了。看来自己的运气还是不错啊)
 
三、解压安装
U-BOOT-1.3.2直接解压就可以了
tar –jxf u-boot-1.3.2.tar.bz2
ELDK则需要通过虚拟光驱来安装。我是用VM来运行LINUX,所以直接用虚拟光驱load就可以了。进入光驱目录,输入
./install –d /opt/eldk/
不到五分钟就可以安装完成了。记得在/etc/profile里面加入搜索路径。
 
四、开始移植
1)        拷贝一份B2板的数据。
分析之后发现原来B2板跟ARMSYS 44B0的板最接近,就从它开始着手吧。
[root@localhost u-boot-1.3.2]# mkdir board/armsys
[root@localhost u-boot-1.3.2]# cp -r board/dave/* board/armsys/
[root@localhost u-boot-1.3.2]# mv board/armsys/B2/ board/armsys/44B0/
[root@localhost u-boot-1.3.2]# mv board/armsys/44B0/B2.c board/armsys/44B0/44B0.c
[root@localhost u-boot-1.3.2]# cp include/configs/B2.h include/configs/44B0.h
2)        修改主Makefile,增加44B0选项
打开u-boot-1.3.2目录下面的Makefile,在B2_config下面增加一项
44B0_config   :      unconfig
       @$(MKCONFIG) $(@:_config=) arm s3c44b0 44B0 armsys
(记着需要用用TAB代替空格!)
3)        修改CPU的配置
现在需要修改44B0的配置了。U-BOOT-1.3.2在CPU的目录下面已经给很多CPU进行分类管理,只要修改一下就能用了。我们选S344B0的CPU。根据LIYUTAI的源代码,我们只需修改相应的部分就可以了。
A.        修改start.s文件(参照LIYUTAI的BOOTLOADER)
#include
#include
 
//**********OPTIONS*******************************
//_RAM_STARTADDRESS  EQU   0xc000000
#define _ISR_STARTADDRESS     0xc7ff000        //GCS6:8MB SDRAM
#define _IRQ_BASEADDRESS      0xc000000      //GCS6:8MB SDRAM
 
//GBLA   PLLCLK
#define PLLCLK    64000000
 
//系统主频计算公式如下:
//Fout = (8+ M_DIV)*Fin/[(2+P_DIV)*2]
#define M_DIV      56    //Fin=8MHz Fout = ((56+8)/8)*8 =64MHz
#define P_DIV       2
#define S_DIV       1
 
 
/*
 * Jump vector table
 */
 
 
.globl _start
_start:
    b      reset                      //    Reset
    ldr    pc, =(_IRQ_BASEADDRESS + 0x04)    //    HandlerUndef
    ldr    pc, =(_IRQ_BASEADDRESS + 0x08)    //    HandlerSWI
    ldr    pc, =(_IRQ_BASEADDRESS + 0x0C)    //    HandlerPabort
    ldr    pc, =(_IRQ_BASEADDRESS + 0x10)    //    HandlerDAbort
    ldr    pc, =(_IRQ_BASEADDRESS + 0x14)    //    HandlerReserved
    ldr    pc, =(_IRQ_BASEADDRESS + 0x18)    //    HandlerIRQ
    ldr    pc, =(_IRQ_BASEADDRESS + 0x1C)    //    HandlerFIQ
 
       .balignl 16,0xdeadbeef
 
 
/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate u-boot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */
 
_TEXT_BASE:
       .word      TEXT_BASE
 
.globl _armboot_start
_armboot_start:
       .word _start
 
/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
       .word __bss_start
 
.globl _bss_end
_bss_end:
       .word _end
 
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
       .word      0x0badc0de
 
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
       .word 0x0badc0de
#endif
 
 
/*
 * the actual reset code
 */
 
reset:
       /*
        * set the cpu to SVC32 mode
        */
       mrs  r0,cpsr
       bic   r0,r0,#0x1f
       orr   r0,r0,#0x13
       msr  cpsr,r0
 
       /*
        * we do sys-critical inits only at reboot,
        * not when booting from ram!
        */
 
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
       bl     cpu_init_crit
       /*
        * before relocating, we have to setup RAM timing
        * because memory timing is board-dependend, you will
        * find a lowlevel_init.S in your board directory.
        */
       bl     lowlevel_init
#endif
 
/**
 * test the memory befor relocate
 */
#ifdef CONFIG_MEM_TEST
#define PDATE      0x1d2002c
       ldr r0,     =PHYS_SDRAM_1              //地址指针
       ldr r1,     =PHYS_SDRAM_1_SIZE     //地址边界
       add r1,r0,r1    //r1 is the bound
       ldr r3,=0xAA55AA44
loop:
       str r3,[r0]                     //保存数据到内存
       ldr r4,[r0]                     //重新读取数据
       cmp r4,r3                     //比较数据
       bne  error
       add r0,r0,#4           //指向下一个指针
       cmp r0,r1                     //判断是否到达边界
       beq mem_test_ok
       bne loop
 
error:
       ldr r0,=PDATE              //PDATE=PDATE&0x1f7;
       ldr r1,[r0]
       ldr r2,=0x1f7
       and r1,r1,r2
       str r1,[r0]
       bl     delay                     //Beep
 
       ldr r1,[r0]                     //PDATE=PDATE|0x8;
       mov r2,#0x8
       orr r1,r1,r2
       str r1,[r0]
       bl     delay                     //stop Beep
end:
       b     end                       //stop
delay:
       ldr r3,=0xFFFF
e_loop1:
       sub r3,r3,#1
       cmp r3,#0
       beq loop_end
       ldr r4,=0xFF
e_loop2:
       sub r4,r4,#1
       cmp r4,#0
       bne e_loop2
       b     e_loop1
loop_end:
       mov pc,lr
 
mem_test_ok:
 
#endif
 
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate:                       /* relocate U-Boot to RAM        */
       adr   r0, _start        /* r0 <- current position of code   */
       ldr   r1, _TEXT_BASE         /* test if we run from flash or RAM */
       cmp     r0, r1                  /* don't reloc during debug         */
       beq     stack_setup
 
       ldr   r2, _armboot_start
       ldr   r3, _bss_start
       sub  r2, r3, r2        /* r2 <- size of armboot            */
       add  r2, r0, r2        /* r2 <- source end address         */
 
copy_loop:
       ldmia       r0!, {r3-r10}         /* copy from source address [r0]    */
       stmia       r1!, {r3-r10}         /* copy to   target address [r1]    */
       cmp r0, r2                    /* until source end addreee [r2]    */
       ble   copy_loop
 
/*
       now copy to sram the interrupt vector
*/
       adr   r0, real_vectors
       add  r2, r0, #1024
       ldr   r1, =0x0c000000
       add  r1, r1, #0x08
vector_copy_loop:
       ldmia       r0!, {r3-r10}
       stmia       r1!, {r3-r10}
       cmp r0, r2
       ble   vector_copy_loop
#endif     /* CONFIG_SKIP_RELOCATE_UBOOT */
 
       /* Set up the stack                                         */
stack_setup:
       ldr   r0, _TEXT_BASE         /* upper 128 KiB: relocated uboot   */
       sub  r0, r0, #CFG_MALLOC_LEN       /* malloc area                      */
       sub  r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
#ifdef CONFIG_USE_IRQ
       sub  r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
       sub  sp, r0, #12             /* leave 3 words for abort-stack    */
 
clear_bss:
       ldr r0, _bss_start          /* BSS段的起始地址 */
       ldr r1, _bss_end           /* BSS段的结束地址 */
       mov r2, #0x00000000   /* BSS段置0 */
clbss_l:
       str r2, [r0]                   /* 循环清除BSS段 */
       add r0, r0, #4
       cmp r0, r1
       ble clbss_l
 
       ldr   pc, _start_armboot
 
_start_armboot:      .word start_armboot
 
 
/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
 
#define INTCON (0x01c00000+0x200000)
#define INTMSK (0x01c00000+0x20000c)
#define LOCKTIME (0x01c00000+0x18000c)
#define PLLCON (0x01c00000+0x180000)
#define CLKCON (0x01c00000+0x180004)
#define WTCON (0x01c00000+0x130000)
cpu_init_crit:
       /* disable watch dog */
       ldr   r0, =WTCON
       ldr   r1, =0x0
       str   r1, [r0]
 
       /*
        * mask all IRQs by clearing all bits in the INTMRs
        */
       ldr   r1,=INTMSK
       ldr   r0, =0x07fffeff
       str   r0, [r1]
 
       ldr   r1, =INTCON
       ldr   r0, =0x05
       str   r0, [r1]
 
       /* Set Clock Control Register */
    ldr   r0,=LOCKTIME
    ldr   r1,=0xfff
    str   r1,[r0]
 
       ldr   r1, =PLLCON
 
#if CONFIG_S3C44B0_CLOCK_SPEED==66
       ldr   r0, =0x34031        /* 66MHz (Quartz=11MHz) */
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
       ldr   r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
#elif CONFIG_S3C44B0_CLOCK_SPEED==64
       ldr   r0, =0x38021  //Fin=8MHz,Fout=64MHz
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif
 
       str   r0, [r1]
 
       ldr   r1,=CLKCON
       ldr   r0, =0x7ff8
       str   r0, [r1]
 
       mov pc, lr
 
 
/*************************************************/
/*    interrupt vectors     */
/*************************************************/
real_vectors:
       b     reset
       b     undefined_instruction
       b     software_interrupt
       b     prefetch_abort
       b     data_abort
       b     not_used
       b     irq
       b     fiq
 
/*************************************************/
 
undefined_instruction:
       mov r6, #3
       b     reset
 
software_interrupt:
       mov r6, #4
       b     reset
 
prefetch_abort:
       mov r6, #5
       b     reset
 
data_abort:
       mov r6, #6
       b     reset
 
not_used:
       /* we *should* never reach this */
       mov r6, #7
       b     reset
 
irq:
       mov r6, #8
       b     reset
 
fiq:
       mov r6, #9
       b     reset
 
B.        修改serial.c,修改serial_setbrg。函数由于板上的波特率使用64MHz,所以需要增加相应的波特率配置
void serial_setbrg (void)
{
       u32 divisor = 0;
 
       /* get correct divisor */
       switch(gd->baudrate) {
 
       case 1200:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
              divisor = 3124;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
              divisor = 3905;
#elif CONFIG_S3C44B0_CLOCK_SPEED==64
              divisor = 3124;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif
              break;
 
       case 9600:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
              divisor = 390;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
              divisor = 487;
#elif CONFIG_S3C44B0_CLOCK_SPEED==64
              divisor = 390;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif
              break;
 
       case 19200:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
              divisor = 194;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
              divisor = 243;
#elif CONFIG_S3C44B0_CLOCK_SPEED==64
              divisor = 194;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif
              break;
 
       case 38400:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
              divisor = 97;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
              divisor = 121;
#elif CONFIG_S3C44B0_CLOCK_SPEED==64
              divisor = 97;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif     /* break; */
 
       case 57600:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
              divisor = 64;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
              divisor = 80;
#elif CONFIG_S3C44B0_CLOCK_SPEED==64
              divisor = 68;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif     /* break; */
 
       case 115200:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
              divisor = 32;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
              divisor = 40;
#elif CONFIG_S3C44B0_CLOCK_SPEED==64
              divisor = 34;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif     /* break; */
       }
 
       serial_flush_output();
       serial_flush_input();
       UFCON0 = 0x0;
       ULCON0 = 0x03;
       UCON0 = 0x245;
       UBRDIV0 = divisor;
 
       UFCON1 = 0x0;
       ULCON1 = 0x03;
       UCON1 = 0x245;
       UBRDIV1 = divisor;
 
       for(divisor=0; divisor<100; divisor++) {
              /* NOP */
       }
}
至此,CPU配置完成。下一步,修改电路板配置。
 
4)        进入armsys/44B0文件夹,开始配置44B0电路板。
A.        修改lowlevel_init.S。lowlevel_init.S是有关外部设备的读写时序、延时的配置文件,可以用LIYUTAI的配置就可以了。(LIYUTAI的RAM配置不是太好,但是还能勉强用上,只是慢一点点而已。)
.equ    B0_Tacs,      0x0 /* 0clk */
.equ    B0_Tcos,      0x1 /* 0clk */
.equ    B0_Tacc,      0x6 /* 10clk */
.equ    B0_Tcoh,      0x1 /* 0clk */
.equ    B0_Tah,       0x0 /* 0clk */
.equ    B0_Tacp,      0x0 /* 0clk */
.equ    B0_PMC,       0x0 /* normal(1data) */
/* Bank 1 parameter */
.equ    B1_Tacs,      0x3 /* 4clk */
.equ    B1_Tcos,      0x3 /* 4clk */
.equ    B1_Tacc,      0x7 /* 14clkv */
.equ    B1_Tcoh,      0x3 /* 4clk */
.equ    B1_Tah,       0x3 /* 4clk */
.equ    B1_Tacp,      0x3 /* 6clk */
.equ    B1_PMC,       0x0 /* normal(1data) */
 
/* Bank 2 parameter */
.equ    B2_Tacs,      0x3 /* 4clk */
.equ    B2_Tcos,      0x3 /* 4clk */
.equ    B2_Tacc,      0x7 /* 14clk */
.equ    B2_Tcoh,      0x3 /* 4clk */
.equ    B2_Tah,       0x3 /* 4clk */
.equ    B2_Tacp,      0x3 /* 6clk */
.equ    B2_PMC,       0x0 /* normal(1data) */
 
/* Bank 3 parameter */
.equ    B3_Tacs,      0x3 /* 4clk */
.equ    B3_Tcos,      0x3 /* 4clk */
.equ    B3_Tacc,      0x7 /* 14clk */
.equ    B3_Tcoh,      0x3 /* 4clk */
.equ    B3_Tah,       0x3 /* 4clk */
.equ    B3_Tacp,      0x3 /* 6clk */
.equ    B3_PMC,       0x0 /* normal(1data) */
 
/* Bank 4 parameter */
.equ    B4_Tacs,      0x3 /* 4clk */
.equ    B4_Tcos,      0x3 /* 4clk */
.equ    B4_Tacc,      0x7 /* 14clk */
.equ    B4_Tcoh,      0x3 /* 4clk */
.equ    B4_Tah,       0x3 /* 4clk */
.equ    B4_Tacp,      0x3 /* 6clk */
.equ    B4_PMC,       0x0 /* normal(1data) */
 
/* Bank 5 parameter */
.equ    B5_Tacs,      0x3 /* 4clk */
.equ    B5_Tcos,      0x3 /* 4clk */
.equ    B5_Tacc,      0x7 /* 14clk */
.equ    B5_Tcoh,      0x3 /* 4clk */
.equ    B5_Tah,       0x3 /* 4clk */
.equ    B5_Tacp,      0x3 /* 6clk */
.equ    B5_PMC,       0x0 /* normal(1data) */
 
/* Bank 6(if SROM) parameter */
.equ    B6_Tacs,      0x3 /* 4clk */
.equ    B6_Tcos,      0x3 /* 4clk */
.equ    B6_Tacc,      0x7 /* 14clk */
.equ    B6_Tcoh,      0x3 /* 4clk */
.equ    B6_Tah,       0x3 /* 4clk */
.equ    B6_Tacp,      0x3 /* 6clk */
.equ    B6_PMC,       0x0 /* normal(1data) */
 
/* Bank 7(if SROM) parameter */
.equ    B7_Tacs,      0x3 /* 4clk */
.equ    B7_Tcos,      0x3 /* 4clk */
.equ    B7_Tacc,      0x7 /* 14clk */
.equ    B7_Tcoh,      0x3 /* 4clk */
.equ    B7_Tah,       0x3 /* 4clk */
.equ    B7_Tacp,      0x3 /* 6clk */
.equ    B7_PMC,       0x0 /* normal(1data) */
 
/* Bank 6 parameter */
.equ    B6_MT,        0x3 /* SDRAM */
.equ    B6_Trcd,      0x1 /* 2clk */
.equ    B6_SCAN,      0x0 /* 10bit */
 
.equ    B7_MT,        0x3 /* SDRAM */
.equ    B7_Trcd,      0x1 /* 2clk */
.equ    B7_SCAN,      0x0 /* 10bit */
 
 
/* REFRESH parameter */
.equ    REFEN,                 0x1 /* Refresh enable */
.equ    TREFMD,                     0x0 /* CBR(CAS before RAS)/Auto refresh */
.equ    Trp,                0x1 /* 2clk */
.equ    Trc,                0x1 /* 0x1=5clk 0x3=11clk*/
.equ    Tchr,               0x2 /* 0x2=3clk 0x0=0clks  */
.equ    REFCNT,               1050 //;period=15.6us, MCLK=64Mhz
 
MEMORY_CONFIG:
  .long   0x11010101 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
  .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
  .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
  .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
  .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
  .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
  .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
  .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  /*GCS6*/
  .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  /*GCS7*/
  .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
  .word 0x17      /*SCLK power down mode, BANKSIZE 16M/16M*/
  .word 0x20      /*MRSR6 CL=2clk*/
  .word 0x20      /*MRSR7*/
 
B.        修改44B0.c文件里面的board_init函数,这个函数是U-BOOT完成底层初始化之后进入的第一个C函数。
int board_init (void)
{
       //CAUTION:Follow the configuration order for setting the ports.
       // 1) setting value
        // 2) setting control register
        // 3) configure pull-up resistor.
 
       //16bit data bus configuration
 
       // PORT A GROUP
       /*  BIT    9 8     7     6     5     4     3     2     1     0     */
       /*        A24      A23 A22 A21 A20 A19 A18 A17 A16 A0   */
       /*        1          1     1     1     1     1     1     1     1     1     */
       PCONA = 0x3ff;
 
       // PORT B GROUP
       /*  BIT 10     9            8            7            6            5            4            3            2            1            0            */
       /*    /CS5       /CS4       /CS3       /CS2       /CS1       nWBE3   nWBE2   /SRAS     /SCAS     SCLK      SCKE      */
       /*    EXT              NIC        USB        IDE        SMC              NC         NC         Sdram     Sdram     Sdram       Sdram     */
       /*      1,        1,   1,   1,    1,    1,       1,     1,    1,    1,   1          */
       PDATB = 0x7ff;
       PCONB = 0x7cf;
 
       //PORT C GROUP
       //BUSWIDTH=16                                                                                       */
       /*  PC15       14           13           12           11           10           9            8     */
       /*    I             O            RXD1     TXD1     I             I             I             I      */
       /* PS2DAT     DCLK     Uart1      Uart1      NC         NC         NC         NC  */
       /*   00          01           11           11           00           00           00           00    */
 
       /*  PC7         6            5            4            3            2            1            0     */
       /*   I            I             I             I             I             I             I             I      */
       /*   VD4       VD5        VD6        VD7        SMCALE SMCCLE SMCCE   SMCRB*/
       /*   00          00           00           00           01           01           01           00    */
       PDATC = 0xffff;    //All IO is high
       PCONC = 0x1f05ff54;
       PUPC  = 0x3000;  //PULL UP RESISTOR should be enabled to I/O
 
       //PORT D GROUP
       /*  PORT D GROUP(I/O OR LCD)                                                                   */
       /*  BIT  7            6            5            4            3            2            1            0     */
       /*  VF          VM         VLINE    VCLK     VD3        VD2        VD1        VD0 */
       /*       00            00           00           00           00           00           00           00    */
       PDATD= 0xff;
       PCOND= 0xaaaa;
       PUPD = 0x0;
       //These pins must be set only after CPU's internal LCD controller is enable
 
       //PORT E GROUP
       /*  Bit 8 7     6     5     4     3     2     1     0     */
       /*      LcdBL     LED4      LED5      LED6      LED7      BEEP      RXD0     TXD0     LcdDisp  */
       /*      01    01    01    01    01    01    10    10    01    */
       PDATE    = 0x1ff;
       PCONE   = 0x25569;
       PUPE      = 0x6;
 
       //PORT F GROUP
       /*  Bit8         7            6            5            4           3            2            1            0            */
       /*  IISCLK    IISDI      IISDO     IISLRCK Input       Input       Input       IICSDA   IICSCL   */
       /*    100         100         100         100         00           00           00           10           10           */
       PDATF = 0x0;
       PCONF = 0x24900a;
       PUPF  = 0x1e3;
 
       //PORT G GROUP
       /*  BIT7        6            5            4            3            2            1            0     */
       /*    INT7             INT6             INT5             INT4             INT3             INT2             INT1             INT0       */
       /*    S3        S4          S5          S6          NIC        EXT              IDE        USB */
       /*      11      11      11      11      11      11      11      11       */
       //rPDATG = 0xff;
       //rPCONG = 0xffff;
       PCONG = 0x00ff; //EXINT0~3 enabled
       PUPG  = 0x0;       //pull-up regiseter should be enabled
 
       SPUCR=0x7;  //D15-D0 pull-up disable
 
       /*均为低电平触发,Exint3设置为上升沿触发----modify at 04-12-11*/
       EXTINT=0x0|(1<<14);
 
       return 0;
}
可以直接使用LIYUTAI的端口初始化函数来代替就可以了。
 
C.        修改Makefile文件,把B2.o替换为44B0.o
 
D.       修改config.mk文件,把TEXT_BASE的值改成0x0C300000。这个只是为了预留2M的空间来下载内核。U-BOOT启动时会把代码拷贝到TEXT_BASE的位置上,如果不修改这个值,下载大一点的代码就会死机的。
 
E.        修改board/armsys/common/flash.c的配置,增加flash支持。
flash.c:
       case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601:
                            并替换所有B2为44B0,这样才能在编译的时候编译进去
 
至此,44B0的电路板已经配置完成。接着就修改配置文件。
 
5)        修改include/configs/44B0.h文件。
以下是我的整个44B0.h配置文件
#ifndef __CONFIG_H
#define __CONFIG_H
 
/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM7                     1     /* This is a ARM7 CPU  */
#define CONFIG_44B0                1     /* on an 44B0 Board      */
#define CONFIG_ARM_THUMB  1     /* this is an ARM7TDMI */
#undef  CONFIG_ARM7_REVD      /* disable ARM720 REV.D Workarounds */
 
#define CONFIG_S3C44B0_CLOCK_SPEED      64 /* we have a 75Mhz S3C44B0*/
 
//#define CONFIG_MEM_TEST                 //do ram test
 
#define CONFIG_SILENT_CONSOLE        1     //config with silent
 
#undef CONFIG_USE_IRQ                 /* don't need them anymore */
 
 
/*
 * Size of malloc() pool
 */
#define CFG_MONITOR_LEN            (256 * 1024)   /* Reserve 256 kB for Monitor      */
#define CFG_ENV_SIZE              1024              /* 1024 bytes may be used for env vars*/
#define CFG_MALLOC_LEN              (CFG_ENV_SIZE + 128*1024 )
#define CFG_GBL_DATA_SIZE    128  /* size in bytes reserved for initial data */
 
/*
 * Hardware drivers
 */
//#define CONFIG_DRIVER_LAN91C96
//#define CONFIG_LAN91C96_BASE         0x04000300 /* base address         */
//#define CONFIG_SMC_USE_32_BIT
//#undef  CONFIG_SHOW_ACTIVITY
//#define CONFIG_NET_RETRY_COUNT         10       /* # of retries          */
#define CONFIG_DRIVER_RTL8019
#define RTL8019_BASE        0x08000000
//#define ET_DEBUG                   //DEBUG the ethernet
 
/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1          1     /* we use Serial line 1 */
 
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
 
#define CONFIG_BAUDRATE             115200
 
/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
 
/*
 * Command line configuration.
 */
#include
 
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
//#define CONFIG_CMD_EEPROM
//#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING                   //ping cmd enable
#define CONFIG_CMD_FLASH          //nor flash support
//#define CONFIG_CMD_NAND                //nand flash support
 
 
#define CONFIG_BOOTDELAY   1
#define CONFIG_ETHADDR       00:50:c2:1e:af:fb
#define CONFIG_BOOTARGS  "setenv bootargs root=/dev/ram ip=192.168.1000.70:::::eth0:off \
       ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
#define CONFIG_NETMASK  255.255.255.0
#define CONFIG_IPADDR   192.168.100.70
#define CONFIG_SERVERIP       192.168.100.163
#define CONFIG_BOOTFILE       "image.ram"
//#define CONFIG_BOOTCOMMAND "bootm 20000 f0000"
//#define CONFIG_BOOTCOMMAND "base 0"          //for debuging
#define CONFIG_BOOTCOMMAND   "?"          //for debuging
 
/*
 * Miscellaneous configurable options
 */
#define    CFG_LONGHELP                       /* undef to save memory              */
#define    CFG_PROMPT             "U-Boot(Ken Wu)>  "   /* Monitor Command Prompt       */
#define    CFG_CBSIZE        256         /* Console I/O Buffer Size     */
#define    CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define    CFG_MAXARGS          16           /* max number of command args  */
#define CFG_BARGSIZE             CFG_CBSIZE /* Boot Argument Buffer Size       */
 
#define CFG_MEMTEST_START 0x0C400000   /* memtest works on     */
#define CFG_MEMTEST_END           0x0C800000   /* 4 ... 8 MB in DRAM  */
 
#undef  CFG_CLKS_IN_HZ              /* everything, incl board info, in Hz */
 
#define    CFG_LOAD_ADDR             0x0c008000    /* default load address   */
 
#define    CFG_HZ                      1000              /* 1 kHz */
 
                                          /* valid baudrates */
#define CFG_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 
/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE     (128*1024)     /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ    (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ     (4*1024) /* FIQ stack */
#endif
 
/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS 1        /* we have 1 banks of DRAM */
#define PHYS_SDRAM_1            0x0C000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE   0x00800000 /* 8 MB */
 
//#define CONFIG_HAS_DATAFLASH               //we have flash
#define PHYS_FLASH_1              0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE        0x00200000 /* 2 MB */
 
//#define CFG_FLASH_BASE              PHYS_FLASH_1
 
/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS    1     /* max number of memory banks         */
#define CFG_MAX_FLASH_SECT      32    /* max number of sectors on one chip  */
#define FLASH_BLOCK_SIZE      0x00010000   //flash的block大小
 
#define CFG_FLASH_ERASE_TOUT   120000    /* Timeout for Flash Erase (in ms)       */
#define CFG_FLASH_WRITE_TOUT  1000       /* Timeout for Flash Write (in ms)       */
 
#define CFG_FLASH_WORD_SIZE     unsigned short       /* flash word size (width)     */
#define CFG_FLASH_ADDR0             0x5555    /* 1st address for flash config cycles   */
#define CFG_FLASH_ADDR1             0x2AAA  /* 2nd address for flash config cycles  */
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0             0x0000    /* 0 is standard                    */
#define CFG_FLASH_READ1             0x0001    /* 1 is standard                    */
#define CFG_FLASH_READ2             0x0002    /* 2 is standard                    */
 
#define CFG_FLASH_EMPTY_INFO          /* print 'E' for empty sector on flinfo */
 
/**
 * NAND flash organization & operation
 */
#if defined(CONFIG_CMD_NAND)
 
#define NAND_DEBUG               1                   //debug the nand info
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE          0x02000000
#define CFG_MAX_NAND_DEVICE   1     /* Max number of NAND devices        */
#define SECTORSIZE 512
 
#define ADDR_COLUMN            1
#define ADDR_PAGE                  2
#define ADDR_COLUMN_PAGE        3
 
#define NAND_ChipID_UNKNOWN   0x00
#define NAND_MAX_FLOORS   1
#define NAND_MAX_CHIPS             1
 
#define NAND_WAIT_READY(nand)   WAIT_RB()
 
#define NAND_DISABLE_CE(nand)    ST_INVALID()
#define NAND_ENABLE_CE(nand)
 
 
#define WRITE_NAND_COMMAND(d, adr)      NAND_write_cmd(d)
//#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
#define WRITE_NAND_ADDRESS(d, adr) NAND_write_addr(d)
#define WRITE_NAND(d, adr)                   NAND_write(d)
#define READ_NAND(adr)                        NAND_read()
/*
 * the following functions are NOP's because S3C24X0 handles this in hardware
 * but it must define in S344B0 board because the board does not support the interface
 */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
 
//do not use write verify and jffs2 ecc at first
//#define CONFIG_MTD_NAND_VERIFY_WRITE   1
//#define CONFIG_MTD_NAND_ECC_JFFS2    1
 
#endif
 
/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
//#define CFG_ENV_IS_IN_EEPROM  1     /* use EEPROM for environment vars */
//#define CFG_ENV_OFFSET             0x0  /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_IS_IN_FLASH              1
#undef CFG_ENV_IS_NOWHERE
#define CFG_FLASH_BASE                PHYS_FLASH_1
#define CFG_ENV_OFFSET               0x100000       //从0x10000处开始保存系统参数
//#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x20000) /* environment start address */
#define CFG_ENV_SECT_SIZE       0x10000              /* Total Size of Environment Sector */
//#define CFG_MONITOR_BASE PHYS_SDRAM_1
 
/*-----------------------------------------------------------------------
 * I2C EEPROM (STM24C02W6) for environment
 */
//#define CONFIG_HARD_I2C                   /* I2c with hardware support */
//#define CFG_I2C_SPEED          400000    /* I2C speed and slave address */
//#define CFG_I2C_SLAVE          0xFE
//
//#define CFG_I2C_EEPROM_ADDR  0xA8       /* EEPROM STM24C02W6         */
//#define CFG_I2C_EEPROM_ADDR_LEN 1     /* Bytes of address        */
///* mask of address bits that overflow into the "EEPROM chip address"   */
///*#define CFG_I2C_EEPROM_ADDR_OVERFLOW       0x07*/
//#define CFG_EEPROM_PAGE_WRITE_BITS 4       /* The Catalyst CAT24WC08 has  */
                                   /* 16 byte page write mode using*/
                                   /* last 4 bits of the address    */
//#define CFG_EEPROM_PAGE_WRITE_DELAY_MS      10   /* and takes up to 10 msec */
//#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
/* Flash banks JFFS2 should use */
/*
#define CFG_JFFS2_FIRST_BANK    0
#define CFG_JFFS2_FIRST_SECTOR 2
#define CFG_JFFS2_NUM_BANKS     1
*/
 
/*
       Linux TAGs (see lib_arm/armlinux.c)
*/
#define CONFIG_CMDLINE_TAG
#undef CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
 
#endif     /* __CONFIG_H */
 
至此,配置已经完成,可以make出镜像来了!!J
 
6)        make镜像
make 44B0_config
make CROSS_COMPILE=arm-linux-
(一大堆编译信息飘过。。。)
最后,你就可以看到u-boot.bin镜像文件了。烧进flash里面就可以直接运行了!^_^
 
五、增加网络支持
由于linux镜像文件动则就有几百k,如果每次都用串口来传就太慢了。LIYUTAI的板子用的是RTL8019,U-BOOT上面直接有驱动,只要改一下就可以用了!(狂喜!!!)
1)        修改drivers/net/rtl8019.h
#include
#include
 
 
#ifdef CONFIG_DRIVER_RTL8019
 
#define ETH_ADDR_SFT (8)
#define EI_SHIFT(x)     ((x)<
 
#define           RTL8019_REG_00                (RTL8019_BASE + EI_SHIFT(0x00))
#define   RTL8019_REG_01                (RTL8019_BASE + EI_SHIFT(0x01))
#define   RTL8019_REG_02                (RTL8019_BASE + EI_SHIFT(0x02))
#define   RTL8019_REG_03                (RTL8019_BASE + EI_SHIFT(0x03))
#define   RTL8019_REG_04                (RTL8019_BASE + EI_SHIFT(0x04))
#define   RTL8019_REG_05                (RTL8019_BASE + EI_SHIFT(0x05))
#define   RTL8019_REG_06                (RTL8019_BASE + EI_SHIFT(0x06))
#define   RTL8019_REG_07                (RTL8019_BASE + EI_SHIFT(0x07))
#define   RTL8019_REG_08                (RTL8019_BASE + EI_SHIFT(0x08))
#define   RTL8019_REG_09                (RTL8019_BASE + EI_SHIFT(0x09))
#define   RTL8019_REG_0a                (RTL8019_BASE + EI_SHIFT(0x0a))
#define   RTL8019_REG_0b                (RTL8019_BASE + EI_SHIFT(0x0b))
#define   RTL8019_REG_0c                (RTL8019_BASE + EI_SHIFT(0x0c))
#define   RTL8019_REG_0d                (RTL8019_BASE + EI_SHIFT(0x0d))
#define   RTL8019_REG_0e                (RTL8019_BASE + EI_SHIFT(0x0e))
#define   RTL8019_REG_0f                 (RTL8019_BASE + EI_SHIFT(0x0f))
#define   RTL8019_REG_10                (RTL8019_BASE + EI_SHIFT(0x10))
#define   RTL8019_REG_1f                 (RTL8019_BASE + EI_SHIFT(0x1f))
 
#define           RTL8019_COMMAND                RTL8019_REG_00
#define           RTL8019_PAGESTART        RTL8019_REG_01
#define           RTL8019_PAGESTOP          RTL8019_REG_02
#define           RTL8019_BOUNDARY         RTL8019_REG_03
#define           RTL8019_TRANSMITSTATUS           RTL8019_REG_04
#define           RTL8019_TRANSMITPAGE        RTL8019_REG_04
#define           RTL8019_TRANSMITBYTECOUNT0 RTL8019_REG_05
#define           RTL8019_NCR                   RTL8019_REG_05
#define           RTL8019_TRANSMITBYTECOUNT1        RTL8019_REG_06
#define           RTL8019_INTERRUPTSTATUS          RTL8019_REG_07
#define           RTL8019_CURRENT           RTL8019_REG_07
#define           RTL8019_REMOTESTARTADDRESS0      RTL8019_REG_08
#define           RTL8019_CRDMA0            RTL8019_REG_08
#define           RTL8019_REMOTESTARTADDRESS1      RTL8019_REG_09
#define           RTL8019_CRDMA1                   RTL8019_REG_09
#define           RTL8019_REMOTEBYTECOUNT0     RTL8019_REG_0a
#define           RTL8019_REMOTEBYTECOUNT1     RTL8019_REG_0b
#define           RTL8019_RECEIVESTATUS        RTL8019_REG_0c
#define           RTL8019_RECEIVECONFIGURATION      RTL8019_REG_0c
#define           RTL8019_TRANSMITCONFIGURATION   RTL8019_REG_0d
#define           RTL8019_FAE_TALLY         RTL8019_REG_0d
#define           RTL8019_DATACONFIGURATION     RTL8019_REG_0e
#define           RTL8019_CRC_TALLY               RTL8019_REG_0e
#define           RTL8019_INTERRUPTMASK             RTL8019_REG_0f
#define           RTL8019_MISS_PKT_TALLY             RTL8019_REG_0f
#define           RTL8019_PHYSICALADDRESS0 RTL8019_REG_01
#define   RTL8019_PHYSICALADDRESS1 RTL8019_REG_02
#define           RTL8019_PHYSICALADDRESS2 RTL8019_REG_03
#define           RTL8019_PHYSICALADDRESS3 RTL8019_REG_04
#define           RTL8019_PHYSICALADDRESS4 RTL8019_REG_05
#define           RTL8019_PHYSICALADDRESS5 RTL8019_REG_06
#define           RTL8019_MULTIADDRESS0             RTL8019_REG_08
#define           RTL8019_MULTIADDRESS1             RTL8019_REG_09
#define           RTL8019_MULTIADDRESS2             RTL8019_REG_0a
#define           RTL8019_MULTIADDRESS3             RTL8019_REG_0b
#define           RTL8019_MULTIADDRESS4             RTL8019_REG_0c
#define           RTL8019_MULTIADDRESS5             RTL8019_REG_0d
#define           RTL8019_MULTIADDRESS6             RTL8019_REG_0e
#define           RTL8019_MULTIADDRESS7             RTL8019_REG_0f
#define           RTL8019_DMA_DATA         RTL8019_REG_10
#define           RTL8019_RESET                 RTL8019_REG_1f
 
 
#define   RTL8019_PAGE0                    0x22
#define         RTL8019_PAGE1                    0x62
#define         RTL8019_PAGE0DMAWRITE              0x12
#define         RTL8019_PAGE2DMAWRITE              0x92
#define         RTL8019_REMOTEDMAWR              0x12
#define         RTL8019_REMOTEDMARD               0x0A
#define         RTL8019_ABORTDMAWR                 0x32
#define         RTL8019_ABORTDMARD                 0x2A
#define         RTL8019_PAGE0STOP              0x21
#define         RTL8019_PAGE1STOP              0x61
#define         RTL8019_TRANSMIT              0x26
#define         RTL8019_TXINPROGRESS        0x04
#define         RTL8019_SEND                      0x1A
 
#define           RTL8019_PSTART               0x4c
#define           RTL8019_PSTOP                0x80
#define           RTL8019_TPSTART                   0x40
 
 
#endif /*end of CONFIG_DRIVER_RTL8019*/
 
2)        修改drivers/net/rtl8019.c
调试网络的时候一直不通,后来调试之后发现原来是rtl8019.c出问题了。不知道为什么put_reg函数就有volatile而get_reg就没有,问题就出现在这里了。加上去,OK!
static unsigned char get_reg (unsigned int regno)
{
       return (*(volatile unsigned char *) regno);
}
 
六、调试U-BOOT
为了调试U-BOOT,我真的详尽了办法,试了好多种方法都不能进行源码级的调试。后来发现了用RVDK可以在window下面进行调试,方法如下:(后来发现原来可以用skyeye来调试,连板子都可以不用上!谢谢skyeye的做着为我们提供这么好的平台)
修改arm_config.mk文件,增加-gdwarf选项
#PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
 
#debug
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ -gdwarf-2
              接着在RVDK上面就可以进行源码级的调试了。爽啊~~~
七、后记
在此要谢谢samfei的移植文档(),基本上对照着就能够完成u-boot-1.1.6。现在我把它移植到1.3.2,希望对新手有帮助。如果手上没有补丁文件,可以来信索取(E-mail: )
 
2008-06-30 于佛山
 
八、附:打补丁的方法
取得补丁之后,可以直接给U-BOOT打补丁,直接得到需要的目标。
 
1)        把补丁文件放到与U-BOOT目录同级的位置
2)        进入U-BOOT目录
[root@localhost ken]# cd u-boot-1.3.2
[root@localhost u-boot-1.3.2]#
3)        打补丁(如果文件是gz格式)
[root@localhost u-boot-1.3.2]# gzip -dc ../u-boot-1.3.2-kenwucn.patch.gz | patch -p1
(以下为终端输出信息)
patching file arm_config.mk
patching file board/armsys/44B0/44B0.c
patching file board/armsys/44B0/config.mk
patching file board/armsys/44B0/flash.c
patching file board/armsys/44B0/lowlevel_init.S
patching file board/armsys/44B0/Makefile
patching file board/armsys/44B0/u-boot.lds
patching file board/armsys/common/flash.c
patching file board/armsys/common/fpga.c
patching file board/armsys/common/nand.c
patching file board/armsys/common/nand.h
patching file board/armsys/common/pci.c
patching file board/bf533-ezkit/.gitignore
patching file board/bf533-stamp/.gitignore
patching file board/bf537-stamp/.gitignore
patching file board/bf561-ezkit/.gitignore
patching file common/cmd_mem.c
patching file common/cmd_nand.c
patching file common/cmd_net.c
patching file common/dlmalloc.c
patching file cpu/s3c44b0/interrupts.c
patching file cpu/s3c44b0/serial.c
patching file cpu/s3c44b0/start.S
patching file drivers/mtd/nand/nand.c
patching file drivers/mtd/nand/nand_ids.c
patching file drivers/mtd/nand_legacy/nand_legacy.c
patching file drivers/net/8390.h
patching file drivers/net/ne2000.c
patching file drivers/net/ne2000.h
patching file drivers/net/rtl8019.c
patching file drivers/net/rtl8019.h
patching file examples/.gitignore
patching file .gdbtkinit
patching file .gitignore
patching file include/configs/44B0.h
patching file include/.gitignore
patching file include/linux/mtd/nand_ids.h
patching file include/net.h
patching file Makefile
patching file net/eth.c
patching file net/Makefile
patching file net/net.c
patching file net/tftp.c
patching file tools/.gitignore
4)        打补丁(如果文件是文本格式(以patch结尾))
[root@localhost u-boot-1.3.2]# patch -p1 < ../u-boot-1.3.2-kenwucn.patch
(以下为终端输出信息)
patching file arm_config.mk
patching file board/armsys/44B0/44B0.c
patching file board/armsys/44B0/config.mk
patching file board/armsys/44B0/flash.c
patching file board/armsys/44B0/lowlevel_init.S
patching file board/armsys/44B0/Makefile
patching file board/armsys/44B0/u-boot.lds
patching file board/armsys/common/flash.c
patching file board/armsys/common/fpga.c
patching file board/armsys/common/nand.c
patching file board/armsys/common/nand.h
patching file board/armsys/common/pci.c
patching file board/bf533-ezkit/.gitignore
patching file board/bf533-stamp/.gitignore
patching file board/bf537-stamp/.gitignore
patching file board/bf561-ezkit/.gitignore
patching file common/cmd_mem.c
patching file common/cmd_nand.c
patching file common/cmd_net.c
patching file common/dlmalloc.c
patching file cpu/s3c44b0/interrupts.c
patching file cpu/s3c44b0/serial.c
patching file cpu/s3c44b0/start.S
patching file drivers/mtd/nand/nand.c
patching file drivers/mtd/nand/nand_ids.c
patching file drivers/mtd/nand_legacy/nand_legacy.c
patching file drivers/net/8390.h
patching file drivers/net/ne2000.c
patching file drivers/net/ne2000.h
patching file drivers/net/rtl8019.c
patching file drivers/net/rtl8019.h
patching file examples/.gitignore
patching file .gdbtkinit
patching file .gitignore
 
patching file include/configs/44B0.h
patching file include/.gitignore
patching file include/linux/mtd/nand_ids.h
patching file include/net.h
patching file Makefile
patching file net/eth.c
patching file net/Makefile
patching file net/net.c
patching file net/tftp.c
patching file tools/.gitignore

本文来自CSDN博客,转载请标明出处:http://blog.csdn.net/wchq1/archive/2008/07/01/2601129.aspx
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