全部博文（25）
分类： LINUX
2011-01-19 13:54:40
/*定义SDRAM相关地址*/
#define ESDCTL_BASE_ADDR 0xB8001000 // base address of SDRAM controller
#define IOMUXC_BASE_ADDR 0x43FAC000 //base address of IO mult register
#define CSD0_BASE_ADDR 0x80000000
#define CSD1_BASE_ADDR 0x90000000
#define RAM_BANK0_BASE CSD0_BASE_ADDR
#define RAM_BANK1_BASE CSD1_BASE_ADDR
ESDCTL_CONFIG: .word 0x007FFC3F
ESDCTL_0xA2210000: .word 0xA2210000
ESDCTL_0xB2210000: .word 0xB2210000
ESDCTL_0x92210000: .word 0x92210000
ESDCTL_0x82216080: .word 0x82216080
setup_sdram_bank:
ldr r0, ESDCTL_BASE_W // ESDCTL_BASE_W内容为0xB8001000
mov r3, #0x2000 //设置SDRAM0/1刷新率为1 Clock
str r3, [r0, #0x0] //设置SDRAM0 控制寄存器
mov r12, #0x00
mov r1, #RAM_BANK0_BASE // 0x80000000
/**************************************************************
* r0: control base
* r1: ram bank base
* r3, r4: working
***************************************************************/
mov r3, #0x30E /*DDR2*/ 0X30E，使能DDR2，使能DDR
str r3, [r0, #0x10]
/**************************************************************
[31] 0 SDRAM/LPDDR external device is not ready for use (reset value).
[9] 1 DDR2 device is used
[8] 1 Non-mobile DDR device is used (DDR2 or DDR1)
[7] 0
[6] 0 MA10 share disable
[5] 0 Latency hiding enable
[4] 1 LPDDR delay line measure unit is disabled.
[3] 1 LPDDR delay line is reset.
[2] 1 DDR SDRAM is used (either mobile or non-mobile).
[1] 1 Soft reset initiated.
***************************************************************/
mov r3, #0x20000 //delay
1: subs r3, r3, #1
bne 1b
adr r4, ESDCTL_CONFIG //设置r4为0x007FFC3F
ldr r3, [r4, #0x0] //DDR2, R3<--0x007FFC3F
str r3, [r0, #0x4] //设置SDRAM0配置寄存器0xB8001004
/***************************************************************
[22:21]tXP=11,4clock after powerdown，
[20]tWTR=1，write to read delay 2clock，
[19:18]Trp=11，row precharge delay4clock
[17:16]tMRD=11，load mode register to active command delay 4 clock
[15]tWR=1，write to precharge command 3clock
[14:12]tRAS = 111，active to precharge command 8clock
[11:10]tRRD=11 ，bank A to active bank B command 4 clocks
[9:8]tCAS=00，CAS latency 3 clocks
[6:4]tRCD=011， row to column delay 4 clocks
[3:0]tRC=1111，row cycle delay 16 clocks
***************************************************************/
ldr r3, ESDCTL_0x92210000 //0x92210000
str r3, [r0, #0x0] //设置SDRAM0控制寄存器ESDCTL0，
/***************************************************************
[31] SDRAM Controller Enable 1
[30-28] SDRAM Controller Operating Mode 001=Precharge Command
[27] Supervisor Protect,disable
[26:24] Row Address Width 010 -13 Row Addresses
[23:22] Reserved
[21:20] Column Address Width 10 -10 Column Addresses
[17:16] SDRAM Memory Data Width 01=16-bit memory width aligned to D[15:0]
SRAM使能，smod为Precharge command，未保护，选择13条行地址，10列地址，16bit数据宽度，
***************************************************************/
ldr r3, ESDCTL_0xA2210000
str r3, [r0, #0x0]
/***************************************************************
[31] SDRAM Controller Enable 1
[30-28] SDRAM Controller Operating Mode 010=Auto-refresh command
[27] Supervisor Protect,disable
[26:24] Row Address Width 010 -13 Row Addresses
[23:22] Reserved
[21:20] Column Address Width 10 -10 Column Addresses
[17:16] SDRAM Memory Data Width 01=16-bit memory width aligned to D[15:0]
SRAM使能，smod为Auto-refresh command，未保护，选择13条行地址，10列地址，16bit数据宽度
***************************************************************/
ldr r3, ESDCTL_0xB2210000
str r3, [r0, #0x0]
/***************************************************************
[31] SDRAM Controller Enable 1
[30-28] SDRAM Controller Operating Mode 011=Load Mode Register Command
[27] Supervisor Protect,disable
[26:24] Row Address Width 010 -13 Row Addresses
[23:22] Reserved
[21:20] Column Address Width 10 -10 Column Addresses
[17:16] SDRAM Memory Data Width 01=16-bit memory width aligned to D[15:0]
SRAM使能，smod为Load Mode Register Command，未保护，选择13条行地址，10列地址，16bit数据宽度
***************************************************************/
mov r3, #0xDA
ldr r4, 0x00000400 //0x00000400
strb r3, [r1, r4] //写一个数据到内存中，为什么？？
ldr r3, ESDCTL_0x82216080
str r3, [r0, #0x0]
/**************************************************************
[31] SDRAM Controller Enable 1
[30-28] SDRAM Controller Operating Mode 000=Normal read/write
[27] Supervisor Protect,disable
[26:24] Row Address Width 010 -13 Row Addresses
[23:22] Reserved
[21:20] Column Address Width 10 -10 Column Addresses
[17:16] SDRAM Memory Data Width 01=16-bit memory width aligned to D[15:0]
[15:13] SDRAM Refresh Rate – P720. 011=4clocks
[11:10] Power Down Timer P721. 00=Disabled (bit field reset value)
[8] Full Page - This bit should be set to 0 if the Burst Length of
// the SDRAM connected to the CSD has been configured to Full-Page mode.
[7] Burst Length. 1=8
[5:0] Precharge Timer. –P722. 000000, Disabled (reset value)
***************************************************************/
