CISCO 千兆器(GSR)体系结构
12012 全总线结构
CISCO GSR仍然是基于对传统路由器的改进，增强了路由器处理器（RP）和增加了专用的ASIC接口处理器。采用接口分布式处理和单一（或冗余）的CPU处理，仍然基于总线结构。
GSR 接口卡
GSR 路由处理器
采用RISC 处理器：
IDT R5000 Reduced Instruction Set Computing (RISC) processor used for the CPU. The CPU runs at an external bus clock speed of 100 MHz and an internal clock speed of 200 MHz.
配置内存包括：
DRAMM—Up to 256 megabytes (MB) of parity-protected, extended data output (EDO) dynamic random-access memory (DRAM) on two, 60-nanosecond (ns), dual in-line memory modules (DIMMs). 128 MB of DRAM is the minimum shipping configuration for the GRP.
SRAM—512 kilobytes (KB) of static random-access memory (SRAM) for secondary CPU cache memory functions. (SRAM is not user configurable or field upgradeable.)
NVRAM—512 KB of nonvolatile RAM (NVRAM). (NVRAM is not user configurable or field upgradeable.)
Memory—Most of the additional memory components used by the system, including onboard Flash memory and up to two Personal Computer Memory Card International Association (PCMCIA)-based Flash memory cards.
Juniper骨干路由器体系结构
体系结构
两个关键部件：Packet Forwarding Engine (PFE)、Routing Engine，, which are connected via a 100-Mbps link.
_ PFE完成分组的转发，包括Flexible PIC Concentrators (FPCs), physical interface cards (PICs), System Control Board (SCB), and state-of-the-art ASICs.
_ Routing Engine维护路由表，控制路由选择。Intel-based PCI platform running JUNOS software.
Leading-edge ASICs
ASICs deliver a comprehensive hardware-based system for packet processing, including route lookups, filtering, sampling, rate limiting, load balancing, buffer management, switching, encapsulation, and de-encapsulation functions. To ensure a non-blocking forwarding path, all channels between the ASICs are oversized, dedicated paths.
Internet Processor II ASIC
The Internet Processor II™ ASIC supports a lookup rate of over 40 Mpps. With over one million gates, the Internet Processor II ASIC delivers high-speed forwarding performance with advanced services, such as filtering and sampling, enabled. It is the largest, fastest, and most advanced ASIC ever implemented on a router platform and deployed in the Internet.
Distributed Buffer Manager ASICs
The Distributed Buffer Manager ASICs allocate incoming data packets throughout shared memory on the FPCs. This singlestage buffering improves performance by requiring only one write to and one read from shared memory. There are no extraneous steps of copying packets from input buffers to output buffers. The shared memory is completely nonblocking, which in turn, prevents head-of-line blocking.
I/O Manager ASICs
Each FPC is equipped with an I/O Manager ASIC that supports packet parsing, packet prioritizing, and queuing. This ASIC divides the packets, stores them in shared memory (managed by the Distributed Buffer Manager ASICs), and reassembles the packets for transmission.
Media-specific ASICs
The media-specific ASICs perform physical layer functions, such as framing. Each PIC is equipped with an ASIC or FPGA that performs control functions tailored to the PIC’s media type.
Packet Forwarding Engine
The PFE provides Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding. The Internet Processor II ASIC forwards up to 40 Mpps for all packet sizes. The throughput is 40+ Gbps.
The PFE supports the same ASIC-based features supported by other M-series routers. For example, class-of-service features include rate limiting, classification, priority queuing, Random Early Detection, and Weighted Round Robin to increase bandwidth efficiency. Filtering and sampling are also available for restricting access, increasing security, and analyzing network traffic.
Finally, the PFE delivers maximum stability during exceptional conditions, while also providing a significantly lower part count. This stability reduces power consumption and increases mean time between failure.
Flexible PIC Concentrators
The FPCs house PICs and connect them to the rest of the PFE. There is a dedicated, full-duplex 3.2-Gbps channel between each FPC and the core of the PFE.
You can insert up to eight FPCs in an M40 chassis. The OC-48c/STM-16 PIC occupies an entire FPC. Otherwise, each FPC supports up to four PICs in any combination, providing unparalleled interface density and configuration flexibility. Each FPC contains shared memory for storing data packets received; the Distributed Buffer Manager ASICs on the SCB manage this memory. In addition, the FPC houses the I/O Manager ASIC, which performs a variety of queue management and class-of-service functions.
Physical Interface Cards
PICs provide a complete range of fiber optic and electrical transmission interfaces to the network. The M40 router offers flexibility and conserves rack space by supporting a wide variety of PICs and port densities. All PICs occupy one of four PIC spaces per FPC except for the OC-48c/STM-16 PIC, which occupies an entire FPC slot. An additional Tunnel Services PIC enables the M40 router to function as the ingress or egress point of an IP-IP unicast tunnel, a Cisco generic routing encapsulation (GRE) tunnel, or a Protocol Independent Multicast - Sparse Mode (PIM-SM) tunnel.
For a list of available PICs, see the M-series Internet Backbone Routers Physical Interface Cards datasheet.
System Control Board
Hosting the Internet Processor II ASIC, the SCB performs sampling, filtering, and packet forwarding decisions. The SCB also houses a processor that processes exception and control packets, monitors system components, and controls FPC resets.
Routing Engine
The Routing Engine maintains the routing tables and controls the routing protocols, as well as the JUNOS software processes that control the router’s interfaces, the chassis components, system management, and user access to the router. These routing and software processes run on top of a kernel that interacts with the PFE. _ The Routing Engine processes all routing protocol updates from the network, so PFE performance is not affected.
_ The Routing Engine constructs and maintains routing tables with a complete set of Internet features and provides full flexibility for advertising, filtering, and modifying routes. Routing policies are set according to route parameters, such as prefixes, prefix lengths, and BGP attributes.
JUNOS Internet Software
JUNOS software is optimized to scale to large numbers of network interfaces and routes. The software consists of a series of system processes running in protected memory on top of an independent operating system. The modular design improves reliability by protecting against system-wide failure and by preventing the failure of one process from affecting the other software processes. JUNOS software offers unmatched configuration flexibility by providing an XML-based JUNOScript™ API in addition to the CLI interface.
总结和观点
【责编:admin】
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