3. ARM Architecture
the ARM is a Rdeuced Instruction Set Computer (RISC) system and includes the attributes typical to that
type of system:
.A large array of uniform registers
.A load/store model
.A small number of addressing modes
.A uniform fixed length instructin (32-bit)
3.1 Processor modes
seven processor modes, most application programs execute in User mode.
-------------------------------------------------------------------------------
Processor mode Description
-------------------------------------------------------------------------------
User usr Normal program execution mode
FIQ faq Fast Interrupt for high-speed data transfer
IRQ irq Used for general-purpose interrupt handling
Supervisor svc A protected mode for the operation system
Abort abt Implements virtual memory and/or memory protection
Undefined und Supports software emulation of hardware coprocessors
System sys Runs privileged operating sysem tasks
( which need access to system resources)
-------------------------------------------------------------------------------
3.2 Registers
+-----------------------------------------------------------------------------------------+
| modes |
| +-------------------------------------------------------------------------------|
| | privileged modes |
| | +----------------------------------------------------------------------|
| | | exception modes |
|---------+--------+----------------------------------------------------------------------|
| User | System | Supervisor| Abort | Undefined | Interrupt | Fast Interrupt |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r0 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r1 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r2 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r3 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r4 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r5 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r6 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r7 | | | | | | |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r8 | | | | | | r8_fiq |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r9 | | | | | | r9_fiq |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r10 | | | | | | r10_fiq |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r11 | | | | | | r11_fiq |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r12 | | | | | | r12_fiq |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r13 | | r13_svc | r13_abt | r13_und | r13_irq | r13_fiq |
|---------+--------+------------+-------------+-------------+------------+----------------|
| r14 | | r14_svc | r14_abt | r14_und | r14_irq | r14_fiq |
|---------+--------+------------+-------------+-------------+------------+----------------|
| pc | | | | | | |
+-----------------------------------------------------------------------------------------+
+---------+--------+------------+-------------+-------------+------------+----------------+
| cpsr | | | | | | |
+---------+--------+------------+-------------+-------------+------------+----------------+
| spsr_svc | spsr_abt | spsr_und | spsr_irq | spsr_fiq |
+----------------------------------------------------------------------+
30 (general) + 6 (status) + 1 (pc)= 37 30 = 15 + 2 + 2 + 2 + 2 + 7
CPSR - Current Processor Status Register
SPSP - Saved Processor Status Register
3.2.1 the Stack pointer, SP or R13
3.2.2 the Link Register,LR or R14
Link Register, it is used to hold the return address for a subroutine.
** when a subroutine call is performed via a BL instrction,R14 is set to the address of the next instruction.
--------------------------------------------------
To return form a subroutine you need to copy the Ling Register into the Program Counter.
two ways:
.Execute eigher of these instructions:
MOV PC,LR
or BAL LR
.On entry to the subroutine store R14 to the stack with an instruction of the form:
STMFD SP!,{,LR}
and use a matching instruction to return from the subroutine:
LDMFD SP!,{,PC}
** when an exception occurs,the execption mode's version of R14 is set to the address
----------------------------------------------------------
after the instruction which has just been completed.
-----------------------------------------------------
3.2.3 the program counter,PC or R15
It is used to identify which instrction is to be performed next.
----
In spite of its name it does not actually count anything!
Reading the program counter
when an instruction reads the PC the value returned is the address of the current instruction plus
8 bytes. (pc=current instruction address + 8 bytes).This is the address of the instruction
after the next instruction to be executed.
----- ----
** avoid to use STR or STM to store R15.
Writing the program counter
When an instruction writes to R15 the normal result is that the value written is treated as an
instruction address and the system starts to execute the instruction at that address.
3.2.4 Current Processor Status Register: CPSR
Because the User and System modes are not exception modes, there is no SPSR available.
CPSR and SPSR format:
31 30 29 28 27 ... 8 7 6 5 4 ... 0
+---+---+---+---+-----------+---+---+-----+-----------+
| N | Z | C | V | SBZ | I | F | SBZ | Mode |
+---+---+---+---+-----------+---+---+-----+-----------+
Negative (N)
Zero (Z)
Carry (C)
Overflow (V)
N: when an operation produces a negative result the negative flag is set and a positive result result results in a the negative flag being reset.
Z: the Zero flag is set when an operation produces a zero result. non-zero result reset it.
C:
V:
S qualitier which instructs the processor to set the condition code flags or not.
3.4 Exceptions
+
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