MIPS Instruction Coding

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Instruction Coding Formats

MIPS instructions are classified into four groups according to their coding formats:

• - This group contains all instructions that do not require an immediate value, target offset, memory address displacement, or memory address to specify an operand. This includes arithmetic and logic with all operands in registers, shift instructions, and register direct jump instructions (jalr and jr).

  All R-type instructions use opcode 000000.

• - This group includes instructions with an immediate operand, branch instructions, and load and store instructions. In the MIPS architecture, all memory accesses are handled by the main processor, so coprocessor load and store instructions are included in this group.

  All opcodes except 000000, 00001x, and 0100xx are used for I-type instructions.

• - This group consists of the two direct jump instructions (j and jal). These instructions require a memory address to specify their operand.

  J-type instructions use opcodes 00001x.

• - MIPS processors all have two standard coprocessors, CP0 and CP1. CP0 processes various kinds of program exceptions. CP1 is a floating point processor. The MIPS architecture makes allowance for future inclusion of two additional coprocessors, CP2 and CP3.

  All coprocessor instructions instructions use opcodes 0100xx.