Memory Addressing （十四）

The Physical Address Extension (PAE) Paging Mechanism

The amount of RAM supported by a processor is limited by the number of address pins connected to the address bus. Older Intel processors from the 80386 to the Pentium used 32-bit physical addresses. In theory, up to 4 GB of RAM could be installed on such systems; in practice, due to the linear address space requirements of User Mode processes, the kernel cannot directly address more than 1 GB of RAM, as we will see in the later section "Paging in Linux."

处理器支持的RAM大小由连接到地址总线的地址管脚的数量决定。早期的Intel处理器（从80386到Pentium）使用32bit物理地址。理论上，这样的系统可支持最大4GB的RAM；实际上，由于用户模式进程对线性地址空间的需求（这句话看不懂，信息量太少），内核不能直接寻址超过1GB的RAM，这将在后面提到。

However, big servers that need to run hundreds or thousands of processes at the same time require more than 4 GB of RAM, and in recent years this created a pressure on Intel to expand the amount of RAM supported on the 32-bit 80x86 architecture.

然而，某些大型服务需要同时运行成百上千个进程，要求使用超过4GB的RAM，在最近几年，这给Intel在32bit的x86架构上扩展对RAM的支持带来了很多压力。

Intel has satisfied these requests by increasing the number of address pins on its processors from 32 to 36. Starting with the Pentium Pro, all Intel processors are now able to address up to 2³⁶ = 64 GB of RAM. However, the increased range of physical addresses can be exploited only by introducing a new paging mechanism that translates 32-bit linear addresses into 36-bit physical ones.

Intel通过将处理器的地址管脚的数目从32增加到36，以应对这样的需求。从Pentium Pro开始，所有Intel处理器都可以寻址高达2^36=64GB的RAM。然而，物理地址范围的扩展必须依赖一种新的页式管理机制，它可以将32bit的线性地址转换到36bit的物理地址。

With the Pentium Pro processor, Intel introduced a mechanism called Physical Address Extension (PAE). Another mechanism, Page Size Extension (PSE-36), was introduced in the Pentium III processor, but Linux does not use it, and we won't discuss it further in this book.

Intel引入了一种新的机制叫做PAE（物理地址扩展）。另一种机制：PSE-36（页面大小扩展）是在Pentium III处理器引入的，但是Linux并没有使用这种机制，我们也不会讨论它。

PAE is activated by setting the Physical Address Extension (PAE) flag in the cr4 control register. The Page Size (PS) flag in the page directory entry enables large page sizes (2 MB when PAE is enabled).

PAE通过设置CR4寄存器的PAE标志启用。页目录项的PS（页面大小）字段可以启用较大的页面大小（当PAE启用时为2MB）。

Intel has changed the paging mechanism in order to support PAE.

Intel为了支持PAE，改变了页式管理的机制：

·         The 64 GB of RAM are split into 2²⁴ distinct page frames, and the physical address field of Page Table entries has been expanded from 20 to 24 bits. Because a PAE Page Table entry must include the 12 flag bits (described in the earlier section "Regular Paging") and the 24 physical address bits, for a grand total of 36, the Page Table entry size has been doubled from 32 bits to 64 bits. As a result, a 4-KB PAE Page Table includes 512 entries instead of 1,024.

          64GB的RAM被分成了2^24个独立的页帧（每页帧2^12=4KB）,页表项的物理地址字段从20bit扩展到了24bit。因为一个PAE页表项必须包含12bit标志位和24bit物理地址，总共36bit，因此页表项的大小就得加倍，从32bit变为64bit。结果一个4KB大的PAE页表包含512项而不是1024项。

·         A new level of Page Table called the Page Directory Pointer Table (PDPT) consisting of four 64-bit entries has been introduced.

           引入了一个新的页表级别称为PDPT（页目录指针表）包含4个64bit大的项。

·         The cr3 control register contains a 27-bit Page Directory Pointer Table base address field. Because PDPTs are stored in the first 4 GB of RAM and aligned to a multiple of 32 bytes (2⁵), 27 bits are sufficient to represent the base address of such tables.

           CR3控制寄存器存储27bit长的PDPT基地址字段。因为PDPT都存储在RAM的头4GB中而且是32byte（2^5）对齐的，因此27bit足够表示这些表的基地址。

·         When mapping linear addresses to 4 KB pages (PS flag cleared in Page Directory entry), the 32 bits of a linear address are interpreted in the following way:

当映射线性地址到4KB大的页时（页目录的PS字段为空），32bit的线性地址被分为下面几部分：

cr3        Points to a PDPT

bits 31-30 Point to 1 of 4 possible entries in PDPT

最高2bit 指向PDPT中的项

bits 29-21 Point to 1 of 512 possible entries in Page Directory

接着9bit 指向页目录中的项

bits 20-12 Point to 1 of 512 possible entries in Page Table

接着9bit 指向页表中的项

bits 11-0  Offset of 4-KB page

最后12bit 4KB页内的偏移

·         When mapping linear addresses to 2-MB pages (PS flag set in Page Directory entry), the 32 bits of a linear address are interpreted in the following way:

当映射线性地址到2MB大的页时（设置了页目录的PS字段），32bit的线性地址被分为下面几部分：

cr3        Points to a PDPT

bits 31-30 Point to 1 of 4 possible entries in PDPT

最高2bit 指向PDPT中的项

bits 29-21 Point to 1 of 512 possible entries in Page Directory

中间9bit 指向页目录中的项

bits 20-0  Offset of 2-MB page

最后21bit 2MB页内的偏移

To summarize, once cr3 is set, it is possible to address up to 4 GB of RAM. If we want to address more RAM, we'll have to put a new value in cr3 or change the content of the PDPT. However, the main problem with PAE is that linear addresses are still 32 bits long. This forces kernel programmers to reuse the same linear addresses to map different areas of RAM. We'll sketch how Linux initializes Page Tables when PAE is enabled in the later section, "Final kernel Page Table when RAM size is more than 4096 MB." Clearly, PAE does not enlarge the linear address space of a process, because it deals only with physical addresses. Furthermore, only the kernel can modify the page tables of the processes, thus a process running in User Mode cannot use a physical address space larger than 4 GB. On the other hand, PAE allows the kernel to exploit up to 64 GB of RAM, and thus to increase significantly the number of processes in the system.

总之，一旦设置了CR3，就可以寻址到4GB大RAM。如果想寻址更大RAM，就不得不设置CR3一个新的值，或者改变PDPT的内容。然而PAE的主要问题就是线性地址仍然只有32bit长。这迫使内核程序员要重用相同的线性地址来映射不同的RAM区域。后面将会讨论启用PAE时Linux是如何初始化页表的。显然，PAE机制并没有增加进程的线性地址空间，因为它仅处理物理地址。还有，只有内核可以修改进程的页表，因此一个在用户模式下运行的进程不能使用超过4GB大的物理地址空间。另一方面，PAE允许内核利用多达64GB的RAM，因此显著地增加了系统内进程的数量。