［原创］Comparison among ARM720T, ARM920T and ARM926E

The ARM720T

The ARM720T is a general-purpose 32-bit RISC processor combining an ARM7TDMI processor core with:

• 32/16-bit RISC architecture (ARMv4T)
• 8 KByte unified cache
• Memory Management Unit (MMU)
• write buffer
• Unified 32-bit AHB bus interface carries both instructions and data
• Embedded Trace Macrocell (ETM) interface

The ARM920T

The ARM920T is a high-performance 32-bit RISC processor combining an ARM9TDMI processor core with:

• 32/16-bit RISC architecture (ARMv4T)
• 16KB instruction and 16KB data caches
• instruction and data Memory Management Units
• write buffer
• AMBA™ (Advanced Microprocessor Bus Architecture)
• Embedded Trace Macrocell (ETM) interface

The ARM926EJ-S

The ARM926EJ-S macrocell is a fully synthesizable 32-bit RISC processor comprising:

• 32/16-bit RISC architecture (ARMv5TEJ)
• ARM9EJ-S Java enhanced processor core
• Flexible instruction and data cache sizes
  
• Memory Management Unit (MMU)
• separate instruction and data AMBA AHB bus Interfaces.
• Tightly-coupled Memory (TCM) interfaces

Comparison

1. Architecture

    ARM720T: ARMv4T instruction set
    ARM920T: ARMv4T instruction set
    ARM926EJ-S: ARMv5TEJ instruction set (Jazelle Java acceleration & DSP instruction extensions)

2. Processor Core

    ARM720T: ARM7TDMI
    ARM920T: ARM9TDMI
    ARM926EJ-S: ARM9EJ-S

3. Cache

    ARM720T: Unified cache (8 KByte)
    ARM920T: Separate instruction and data caches (16KB/16KB)
    ARM926EJ-S: Flexible and separate instruction and data cache sizes

4. MMU

    ARM720T: Unified MMU
    ARM920T: Separate instruction and data MMU
    ARM926EJ-S: Separate instruction and data MMU

5. AMBA AHB Bus Interface

    ARM720T: Unified AHB bus interface (both instructions and data)
    ARM920T: Unified AHB bus interface (both instructions and data)
    ARM926EJ-S: Separate instruction and data AMBA AHB bus Interfaces

6. TCM interfaces

    ARM720T: None
    ARM920T: None
    ARM926EJ-S: Tightly-coupled Memory (TCM) interfaces

7. Pipeline

    ARM720T: Three-stage pipeline
    ARM920T: Five-stage pipeline
    ARM926EJ-S: Five-stage pipeline

    The three-stage:

• F: Instruction Fetch
• D: Instruction Decode
• E: Instruction Execute
  

    The five-stage:

• F: Instruction Fetch
• D: Instruction Decode and Register Read
• E: Execute Shift and ALU, or Address Calculate, or Multiply
• M: Memory Access and Multiply
• W: Register Write