ppc assembly language ppc 汇编

Simplified Mnemonics for PowerPC 555 Assembly
Instruction	Description	Other Registers Altered	Explanation of Operation
add  rD, rA, rB	Add	CR0 (LT, GT, EQ, SO)	rD ＝ rA + rB
addi  rD, rA, value	Add immediate	None	rD ＝ rA + value
addis  rD, rA, value	Add immediate shifted left by 16 bits	None	rD ＝ rA + (value << 16)
and  rA, rS, rB	AND	None	rA ＝ rS & rB
andi.  rA, rS, value	AND Immediate	CR0 (LT, GT, EQ, SO)	rA ＝ rS & value
andis.  rA, rS, value	AND Immediate shifted left by 16 bits	CR0 (LT, GT, EQ, SO)	rA ＝ rS & (value << 16)
b  target_addr	Branch Always	None	Branch to target_addr
ble  target_addr	Branch if less than or equal to (LT or EQ flags of CR0 set)	None	Branch to target_addr if LT = 1 or EQ = 1
blt  target_addr	Branch if less than (LT of CR0 set)	None	Branch to target_addr if LT = 1
beq  target_addr	Branch if equal (EQ of CR0 set)	None	Branch to target_addr if EQ = 1
bge  target_addr	Branch if greater than or equal to (GT or EQ of CR0 set)	None	Branch to target_addr if GT = 1 or EQ = 1
bgt  target_addr	Branch if greater than (GT of CR0 set)	None	Branch to target_addr if GT = 1
blr  target_addr	Branch to LR (Link Register)	None	Branch and link to target_addr
bne  target_addr	Branch if not equal (EQ of CR0 not set)	None	Branch to target_addr if EQ = 0
cmpw  rA, rB	Compare Word	CR0 (LT, GT, EQ, SO)	rA - rB
cmpwi  rA, value	Compare Word Immediate	CR0 (LT, GT, EQ, SO)	rA - value
la  rD, label	Load Address based upon offset value	None	rD ＝ label
lbz  rD, d(rA)	Load Byte and Zero	None	rD ＝ m[rA + d]
lbzx  rD, rA, rB	Load Byte and Zero Indexed	None	rD ＝ m[rA + rB]
lhz  rD, d(rA)	Load Half Word and Zero	None	rD ＝ M[rA +d]15..0
lhzx  rD, rA, rB	Load Half Word and Zero Indexed	None	rD ＝ M[rA +rB]15..0
li  rA, value	Load immediate	None	rA ＝ value
lis  rA, value	Load immediate shifted left by 16 bits	None	rA ＝ (value << 16)
lwz  rD, d(rA)	Load Word and Zero	None	rD ＝ M[rA + d]
lwzx  rD, rA, rB	Load Word and Zero Indexed	None	rD ＝ M[rA + rB] rD = rA + rB
mr  rA, rS	Move Register	None	rA ＝ rS
not  rA, rS	Complement Register (invert)	None	rA ＝ ~rS
ori  rA, rS, value	OR Immediate	None	rA ＝ rS | value
oris  rA, rS, value	OR Immediate shifted left by 16 bits	None	rA ＝ rS | (value << 16)
slwi  rA, rS, value	Shift Left Immediate	None	rA ＝ (rS << value)
srwi  rA, rS, value	Shift Right Immediate	None	rA ＝ (rS >> value)
stb  rS, d(rA)	Store Byte	None	m[rA + d] ＝ rS7..0
stbx  rS, rA, rB	Store Byte Indexed	None	m[rA + rB] ＝ rS7..0 rA = rA + rB
sth  rS, d(rA)	Store Half Word	None	M[rA + d]15..0 =rS15..0
sthx  rS, rA, rB	Store Half Word Indexed	None	M[rA +rB]15..0 =rS15..0
stw  rS, d(rA)	Store Word	None	M[rA + d] = rS
stwx  rS, rA, rB	Store Word Indexed	None	M[rA + rB] = rS
sub  rD, rA, rB	Subtract	None	rD = rA - rB
subi  rD, rA, value	Subtract Immediate	None	rD = rA - value
subis  rD, rA, value	Subtract Immediate shifted left by 16 bits	None	rD = rA - (value << 16)