vhdl实现的8位可逆计数器

vhdl实现的8位可逆计数器

能实现连续脉冲还手动脉冲计数，在实验板上实验过~！

程序很简单，相应的注释就没加了，

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
 port(rst,clk,clk1: in std_logic;
   con : std_logic_vector(1 downto 0);
   output : out std_logic_vector(7 downto 0));
  
end entity counter;

architecture behave of counter is
 begin
 process(rst,con,clk,clk1)
  variable temp1 : std_logic_vector(7 downto 0);
  begin
  if rst = '1' then temp1 := (others => '0');
  else
   case con is
   when "10" =>--手动顺记数
    if clk'event and (clk='1') and (clk'last_value='0') then
      if temp1 < 255 then temp1 := temp1 + 1;
      
       else temp1 := (others => '0');
        
      end if;
    end if;
   when "11"  =>--手动逆记数
    if clk'event and (clk='1') and (clk'last_value='0') then
         if temp1 > 0 then temp1 := temp1 - 1;
          else temp1 := (others => '1');
           
         end if;
     end if;
   when "00" =>--连续顺记数
    if clk1'event and (clk1='1') and (clk1'last_value='0') then
      if temp1 < 255 then temp1 := temp1 + 1;
      
       else temp1 := (others => '0');
        
      end if;
    end if;
   when "01" =>--连续逆记数
    if clk1'event and (clk1='1') and (clk1'last_value='0') then
         if temp1 > 0 then temp1 := temp1 - 1;
          else temp1 := (others => '1');
           
         end if;
    end if;
   end case;
  end if;
 output <= temp1;
 end process;
end architecture behave;