vhdl实现的多循环方式彩灯

vhdl实现的多循环方式彩灯

-----the top file of cyc_led design
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cyc_led is
port(contr : in std_logic_vector(1 downto 0);
  clk : in std_logic;
  light : out std_logic_vector(7 downto 0));
end entity cyc_led;

architecture cyc_light of cyc_led is
 component mode1 is---mode1
  port(clk1 : in std_logic;
    light1 : out std_logic_vector(7 downto 0));
 end component; 
 
 component mode2 is---mode2
  port(clk2 : in std_logic;
    light2 : out std_logic_vector(7 downto 0));
 end component;
 
 component mode3 is ---mode3 
  port(clk3 : in std_logic;
    light3 : out std_logic_vector(7 downto 0));
 end component;
 
 component mode4 is ---mode4
  port(clk4 : in std_logic;
    light4 : out std_logic_vector(7 downto 0));
 end component;
 signal temp1,temp2,temp3,temp4 : std_logic_vector(7 downto 0);
 begin
U1: mode1 port map (clk,temp1);
U2: mode2 port map (clk,temp2);
U3: mode3 port map (clk,temp3);
U4: mode4 port map (clk,temp4);
  process(clk,contr)
  begin
  case contr is
  when "00" => light <= temp1;
   when "01" => light <= temp2;
  when "10" => light <= temp3;
  when "11" => light <= temp4;
 end case;
 end process;
end architecture cyc_light;

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mode1 is
 port(clk1 : in std_logic;
   light1 : out std_logic_vector(7 downto 0));
end entity mode1;
----------------------------------------------
architecture machine1 of mode1 is
 type state is (s0,s1,s2,s3,s4,s5);
 signal cur_state,nex_state: state;
 begin
time: process(clk1)
  begin
  if clk1'event and clk1='1' then cur_state <= nex_state;
  end if;
   end process;
comb: process(cur_state)
  begin
  case cur_state is
   when s0 => light1 <= "11100000";
      nex_state <= s1;
   when s1 => light1 <= "01110000";
      nex_state <= s2;
   when s2 => light1 <= "00111000";
      nex_state <= s3;
   when s3 => light1 <= "00011100";
      nex_state <= s4;
   when s4 => light1 <= "00001110";
      nex_state <= s5;
   when s5 => light1 <= "00000111";
      nex_state <= s0;
  end case;
 end process comb;
end architecture machine1;  

 

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mode2 is
 port(clk2 : in std_logic;
   light2 : out std_logic_vector(7 downto 0));
end entity mode2;
----------------------------------------------
architecture machine2 of mode2 is
 type state is (s0,s1,s2,s3);
 signal cur_state,nex_state: state;
 begin
time: process(clk2)
  begin
  if clk2'event and clk2='1' then cur_state <= nex_state;
  end if;
   end process;
comb: process(cur_state)
  begin
  case cur_state is
   when s0 => light2 <= "11000000";
      nex_state <= s1;
   when s1 => light2 <= "00110000";
      nex_state <= s2;
   when s2 => light2 <= "00001100";
      nex_state <= s3;
   when s3 => light2 <= "00000011";
      nex_state <= s0;   
  end case;
 end process comb;
end architecture machine2;  

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mode3 is
 port(clk3 : in std_logic;
   light3 : out std_logic_vector(7 downto 0));
end entity mode3;
----------------------------------------------
architecture machine3 of mode3 is
 type state is (s0,s1,s2,s3,s4,s5);
 signal cur_state,nex_state: state;
 begin
time: process(clk3)
  begin
  if clk3'event and clk3='1' then cur_state <= nex_state;
  end if;
   end process;
comb: process(cur_state)
  begin
  case cur_state is
   when s0 => light3 <= "10100000";
      nex_state <= s1;
   when s1 => light3 <= "01010000";
      nex_state <= s2;
   when s2 => light3 <= "00101000";
      nex_state <= s3;
   when s3 => light3 <= "00010100";
      nex_state <= s4;
   when s4 => light3 <= "00001010";
      nex_state <= s5;
   when s5 => light3 <= "00000101";
      nex_state <= s0;
  end case;
 end process comb;
end architecture machine3;  

 

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mode4 is
 port(clk4 : in std_logic;
   light4 : out std_logic_vector(7 downto 0));
end entity mode4;
----------------------------------------------
architecture machine4 of mode4 is
 type state is (s0,s1,s2,s3,s4,s5,s6,s7);
 signal cur_state,nex_state: state;
 begin
time: process(clk4)
  begin
  if clk4'event and clk4='1' then cur_state <= nex_state;
  end if;
   end process;
comb: process(cur_state)
  begin
  case cur_state is
   when s0 => light4 <= "10000000";
      nex_state <= s1;
   when s1 => light4 <= "01000000";
      nex_state <= s2;
   when s2 => light4 <= "00100000";
      nex_state <= s3;
   when s3 => light4 <= "00010000";
      nex_state <= s4;
   when s4 => light4 <= "00001000";
      nex_state <= s5;
   when s5 => light4 <= "00000100";
      nex_state <= s6;
   when s6 => light4 <= "00000010";
      nex_state <= s7;
   when s7 => light4 <= "00000001";
      nex_state <= s0;   
  end case;
 end process comb;
end architecture machine4;