lemonoje
Jan 13 2006, 02:39 PM
![ph34r.gif]()
Well - as with many other people from what I've read - I get the old Verify Failure message when trying to download any project including just a hello_world program:
Downloading 00000020 ( 0%)
Downloading 00010000 (71%)
Downloaded 91KB in 1.1s (82.7KB/s)
Verifying 00000020 ( 0%)
Verify failed between address 0x20 and 0xFFFF
Leaving target processor paused
HOW CAN I GET RID OF THIS ERROR - OR CAN I JUST NEVER RUN PROGRAMS AGAIN?
thanks,
baycool
Jan 13 2006, 05:16 PM
Hi Lemonoje,
THere are so many reasons for the Verify fail, that is why it is so popular. ![smile.gif]()
Here are a few that I have seen
1. Bad memory interface, physical board problem
2. Timing issue with memory
3. Lack of non-volatile memory. This confuses processor.
Hope that helps a little.
-Baycool
dannyjacobs
Jan 16 2006, 03:06 AM
Hi Lemonojo,
are you sure you downloaded the right NIOS II into your board...
Cheers,
Danny
lemonoje
Jan 16 2006, 08:41 AM
Well, the memory interface is a straight SDRAM instantiated in SOPC and then all the signals are routed to the chip. The memory in terms of timing works fine because I tested it using LabVIEW making calls to FS2's MDI to perform adderss/data bus tests, etc...
Everything works doing basic R/W peek/pokes from the FS2 CLI. Thanks for the feedback. Any other ideas?
PS - I am also getting Verify Failed from the Nios II flash programmer (from the sdk shell) when trying to load flash. I even tried re-installing Nios II 5.1 - no luck.
atjung
Jan 16 2006, 10:42 PM
If you have problems with downloading programs from the IDE, I suggest to try reconfigure your FPGA with a "simple" test design that is a sub-set of your design. For example to isolate if your problem is SDRAM or SRAM, try to use/add onchip_memory to run hello world from. If the onchip_memory program runs, but loading the program to SDRAM/sram still fails, I would take a closer look at the memory timing or phase setting.
Once feature I've found useful in sorting out a "verify failure" is to have a System ID peripheral (this is found in the SOPC Builder "other" components group) in my system design. This will sort out if I accidentally loaded the wrong system on my development board or if the board gets reset into a "safe" design on a NIOS II dev board.
When I download a program to a board, if I have the wrong system loaded it will flag a different time stamp.
Another useful part of this is if the system ID tag is something odd like FFFF_FFFF, it shows that I could have a hardware issue like:
1) some setting error in my design that is messed up my system like I forgot to set "unused IOs to tri-state" (by default Quartus II will set all unused IOs to drive ground which may cause issues with other componets on the board that are not expecting the FPGA to pull its pins to ground).
2) line noise and my JTAG port needs a pull-up resistor/cap on a signal to handle line noise or I could have a bad USB-blaster etc....
Good luck in isolating the problem
lemonoje
Jan 17 2006, 08:39 AM
I also use the system ID feature to make sure I have the correct hardware. That's a great idea to make some internal RAM to try and run out of. The problem with that may be that the Stratix II (2S15) doesn't have much RAM in it at all (even compared to the lowest Stratix I). I know a hello_world project barely fit into my one Stratix I internal RAM design, and like I said it has much more RAM. Nonetheless, I'll try it.
I am also trying to look at the JTAG signals to see if something looks bad there...
lemonoje
Jan 18 2006, 09:17 AM
Just as an update, I got my programs to download/verify and run again. I originally used the Altera provided calculations to phase shift the SDRAM clock, but I thought I should just try and recalculate everything. When I do this my calculations come out quite different than the Altera example where both of my lead numbers, for example, were negative. So I didn't know if I should take the lesser of the two? Take the absolute value of both and then negate one?
So, what I did was regenerate the system in SOPC, entirely recompile in Quartus, and then recalculate the SDRAM phase shift. I entered this, recompiled in Quartus, and now it seems to be working fine. ![biggrin.gif]()
LiangYi
Jan 19 2006, 02:36 AM
Hi lemonoje,
QUOTE
The memory in terms of timing works fine because I tested it using LabVIEW making calls to FS2's MDI to perform adderss/data bus tests, etc...
But, how do you get the sdram pins work fine? The IDE display download info, then verify failed. Do you know that what will be done in verify process and what is the sdram pins state?
Thank you,
LiangYi
lemonoje
Jan 19 2006, 08:25 AM
QUOTE(LiangYi @ Jan 19 2006, 02:36 AM)
Hi lemonoje,
QUOTE
The memory in terms of timing works fine because I tested it using LabVIEW making calls to FS2's MDI to perform adderss/data bus tests, etc...
But, how do you get the sdram pins work fine? The IDE display download info, then verify failed. Do you know that what will be done in verify process and what is the sdram pins state?
Thank you,
LiangYi
I'm sorry I have no idea what you're asking.
atjung
Jan 19 2006, 05:03 PM
QUOTE(LiangYi @ Jan 19 2006, 12:36 AM)
Hi lemonoje,
QUOTE
The memory in terms of timing works fine because I tested it using LabVIEW making calls to FS2's MDI to perform adderss/data bus tests, etc...
But, how do you get the sdram pins work fine? The IDE display download info, then verify failed. Do you know that what will be done in verify process and what is the sdram pins state?
Thank you,
LiangYi
If I understand what you are asking -- From talking with other users, if you have "boarderline" timing issues with memory doing peeks and pokes to a few memory locations will not always show a problem. Peeks and pokes only help show "major" timming issues or incorrectly connected memories.
If you hit the memory with a large block of data transfers the "boarderline" memory timing issues will start to up. For example
1) A DMA transfer to memory and back shows different results
2) If you load your program into SDRAM memory that has borderline timing issues, the processor is always accessing its next instruction so the memory problems will show up quickly by your program locking up.
3) If you use the IDE download a new program onto your board (writes are ok) and it fails verify (read fails) then one cause could be memory timing or I incorrectly connected the memory.
LiangYi
Jan 20 2006, 01:32 AM
Hi,
I resolve my problem.
I recheck the hardware connect and jointing. I found there has a data pin jointing to gnd. So, I re-solder this pin, now it works OK.
Thank you,
LiangYi
lemonoje
Jan 20 2006, 08:29 AM
QUOTE(atjung @ Jan 19 2006, 05:03 PM)
QUOTE(LiangYi @ Jan 19 2006, 12:36 AM)
Hi lemonoje,
QUOTE
The memory in terms of timing works fine because I tested it using LabVIEW making calls to FS2's MDI to perform adderss/data bus tests, etc...
But, how do you get the sdram pins work fine? The IDE display download info, then verify failed. Do you know that what will be done in verify process and what is the sdram pins state?
Thank you,
LiangYi
If I understand what you are asking -- From talking with other users, if you have "boarderline" timing issues with memory doing peeks and pokes to a few memory locations will not always show a problem. Peeks and pokes only help show "major" timming issues or incorrectly connected memories.
If you hit the memory with a large block of data transfers the "boarderline" memory timing issues will start to up. For example
1) A DMA transfer to memory and back shows different results
2) If you load your program into SDRAM memory that has borderline timing issues, the processor is always accessing its next instruction so the memory problems will show up quickly by your program locking up.
3) If you use the IDE download a new program onto your board (writes are ok) and it fails verify (read fails) then one cause could be memory timing or I incorrectly connected the memory.
This is exactly correct. Peeks and pokes are good for identifying more major issues, although FS2's command line can load programs, etc... which WILL do large blocks of data transfer to test the timing exhaustively. I had been only doing peeks and pokes from the command line and everything seemed fine. Verify was failing, as you put it, becuase of "boarderline" timing.
crisjory
Feb 3 2006, 06:10 AM
I would like to continue this discussion.
My system works fine, but sometimes I do a little change in the vhdl of a periphal and then the ide begins with Verify failed message...
Almost all changes don't cause problems, but a few changes do that and it seems there is no relationship with change in memory map or behavior.
Someone has a trick for that?
crisjory
Feb 3 2006, 08:57 AM
I found it!!
I was using a C0 output pll for the sdram_clk, and sometimes it dont achieve the desired phase shift for the sdram. Now I m using a E0 output pll, it is exclusive for external output pll and dont receive influence from internal routing.
I hope this can help another guys....
lemonoje
Feb 3 2006, 09:13 AM
great - glad you found the problem! That will probably also get rid of the jitter warning error that you get when it has to route internal
Buca
Jul 24 2006, 10:48 AM
QUOTE(lemonoje @ Feb 3 2006, 03:13 PM)
great - glad you found the problem! That will probably also get rid of the jitter warning error that you get when it has to route internal
Hi lemonoje i'm getting started now with a stratix II (EP2S60F1020C4) and i had the same problem :
Verifying 03000020 ( 0%)
Verify failed
Leaving target processor paused.
I solved it by downloading an the board the standard.qpf file that i found i the directory:
altera\kits\StratixII_DSP_Kit-v1.1.0\Examples\HW\NiosII\example_designs\vhdl\standard
I have downloaded this file without compiling it.
I started Nios II IDE and runned a sample project unchecking Validate Nios II System ID before software downolad.
Everything works fine now.Good Luck and sorry if said uncorrect things but i'm not so expert as you are! ![tongue.gif]()
ikuo005
Aug 25 2006, 07:42 AM
Hi lemonje:
I have a question, what calculation did you do to find out the phase shift needed for SDRAM?? Where can I find out more about the calculation for the phase shift ?
I have been using the ALTERA example design all along throughout my project, and it has been fine until recently .
I just made a really huge JPEG decompresssion custom hardware component, I fitted it into the standard design example from Altera and somehow the verification started failing ... ![sad.gif]()
Any idea??
And also i run my jpeg componenet at a different frequency (35Mhz) than my board freq (50Mhz), do you know how can I find out about any clock setup time or hold time I need to configure to read the memmory I built within the jpeg component?
Thanks in advance
Tony
lemonoje
Aug 28 2006, 08:46 AM
Tony,
Check out the "SDRAM Controller with Avalon Interface" data sheet at :
. At the very bottom you will find calculations for this.
With regards to the new component that runs at a different clock frequency than the CPU - have you hardended the signals across clock domains? If I'm understanding, it sounds like you have a 50MHz clock for CPU and a 35MHz clock for the JPEG logic, which would require special care for the signals to cross each other to avoid instability.
I'm very busy now, so sorry if the response time is a while...
ikuo005
Aug 28 2006, 09:24 PM
Hi Lemonoje,
Thank you very much for your reply.
Yes, I found the doc from the Altera website, but I have been having difficulty finding the right tso and th from the compilation report. (i found max and min tco)
I was abit confused about the tsu and th becoz the th and tsu i got from the compilation report are quite different to the ones used in the example calculation in the doc.
For example, for th I had -0.963 for th but it's -5.6 ns in the example. Is this what I should be getting??
I tried -3.5ns shift for my sdram clock, and it seems to work fine. but the phase shift I should be using is actually -1.0ns according to my calculation (I haven't really tried this shift)
Yes, I was running my jpeg unit and NIOS II CPU at a different frequencies (35Mhz&50Mhz) but I decided to get the functionalities right first by running them both at 35 Mhz. It's easier to adjust the timing for SDRAM clock with lower frequency but i am not exactly sure how should I adjust it, more negative or more positive?.
I guess we have to do it through trial and error?
(MY SDRAM is the same as the one used in the example).
I compiled the standard Altera example,( I didn't modify it), and the tsu, th, max tco and min tco i found in the compilation report are :
1.405, -0.963, 4.127 and 2.362. ns
from the calculation using the same SDRAM, I got 2.161/2 ~= 1.0805ns. does this sound right?
Oh and also, do you happen to know that is it necessary to adjust the timing setting such as "issue one refresh command every ___ns", duration of refresh command ...etc if we lower the clock to 35 Mhz ?
Thank you very much.
Tony
mgilroy
Oct 6 2006, 07:56 AM
I tried all the combinations of things to try and fix this problem.
I finally managed to get rid of the verify fail by including the sysid block. Other than that no changes were made. Strange.
bigpunx
Nov 12 2006, 07:20 PM
I am trying to load the uClinux image for the DE2 board. I've loaded the sof and pof and downloaded using the wiki instructions. I keep getting the following message..
Downloading 630KB in 7.7s
Verfying 00500000 <0%>
Verify failed between address 0x500000 and 0x502A19
Anybody know why I can't get this working? I'm using the DE2_NET project and zimage_de2_net files. It should work but for me it doesn't. Please help me make this DE2 board more than a 500$ paper weight that blinks.
hippo
Nov 14 2006, 09:54 AM
QUOTE(bigpunx @ Nov 13 2006, 08:20 AM)
I am trying to load the uClinux image for the DE2 board. I've loaded the sof and pof and downloaded using the wiki instructions. I keep getting the following message..
Downloading 630KB in 7.7s
Verfying 00500000 <0%>
Verify failed between address 0x500000 and 0x502A19
Anybody know why I can't get this working? I'm using the DE2_NET project and zimage_de2_net files. It should work but for me it doesn't. Please help me make this DE2 board more than a 500$ paper weight that blinks.
The sdram address range of de2 is 0-0x00800000.
The zImage will be loaded to 0x00500000.
SO it loaded, but verify failed.
Do you use quartus2 v6.0 sp1, nios2 v6.0 sp1, de2 system disc v1.3 ?
Do you use quaruts2 to config the de2 with DE2_NET.sof before nios2-download?
The config data of fpga will lose when power off.
Have you tried some demo programs from sdram?
kc@xelic.com
Nov 16 2006, 06:52 PM
QUOTE(crisjory @ Feb 3 2006, 09:57 AM)
I found it!!
I was using a C0 output pll for the sdram_clk, and sometimes it dont achieve the desired phase shift for the sdram. Now I m using a E0 output pll, it is exclusive for external output pll and dont receive influence from internal routing.
I hope this can help another guys....
Hello, I am getting the old veriy failed error message. However, I am using the cycloneII Device and i don't think cycloneII supports the E0 output pll. I was wondering what device you were using.
Thank you
