A high speed data acquisition system implements high-speed integrated circuits to trigger and acquire high data rate flow control and storing.
Core Subsystems include: Analog Input Front End - built around a high-speed ADC including high-speed Op-Amps, FIFOs, and SRAMs. The stream of data output from the ADC is written into FIFOs, stored in blocks of SRAM, and sent directly to the outside world through registers under the control of the data acquisition logic in the FPGA. FPGA - contains data acquisition controls and logics including the trigger logic, error detection, DSP interface, memory address decoder, counters, and output control. The control logic selects a data acquisition clock, processes different triggers, and transfers the acquired data to the internal memory of the data acquisition channels. Analog Output - built around a high-speed DAC, including Op-Amp and output data buffer. High-Speed Bus Interface - transfers data through high-speed parallel bus on the back plane (PCI,VMEbus) or high-speed Ethernet. Clock Source - provides clock for different data acquisition options and modes. Power Managements - converts the input power from the backplane to run various functional blocks.
