FPGA中子程序及包集合

library ieee;
use ieee.std_logic_1164.all;

entity mux2 is
 port(a,b,s: in std_logic;
   y : out std_logic);
end mux2;

architecture one of mux2 is
 begin
 process(s,a,b)
 begin
  if s='0' then y<=a;
  else y<=b;
  end if;
 end process;
end one ;

 

********************************************************************

library ieee;
use ieee.std_logic_1164.all;

package my_pkg is 

元件体外配置 

component mux2
 port(a,b,s: in std_logic;
   y: out std_logic);
 end component;
 

过程调用语句
 procedure diff(signal d:bit_vector(7 downto 0);
     signal clk: bit;
     signal q; out bit_vector(7 downto 0));
 
 begin
 wait until clk='1';
 q<=d;
 end diff;
 

子函数声明
 FUNCTION odd_par8(di: std_logic_vector(7 downto 0))
   return std_logic is
   variable temp: std_logic;
   begin
    temp:='0';
    for k in 7 downto 0 loop
     temp := di(k) xor temp;
    end loop;
   return temp;
 end odd_par8;
  
end my_pkg;

**********************************************************************

如果调用my_pkg  只需要use work.my_pkg.all就可以调用自己声明的各种函数或变量等。