你撒下一粒善良的种_子， 会在暗中蔓延出一片灿烂的花海
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2008-04-28 11:42:29
A multiple-bit wire name can be a bundle, a bus, or a combination of the two. You can improve readability in your designs by shortening multiple-bit wire names.
To indicate that multiple bits of one wire carry similar information, give each bit the same base name. Then add a suffix to each bit name to distinguish the signals.
For example, to show four bits of a wire with a common base name (DATA), but with individual suffixes (<0>, <1>, <2>, and <3>), assign the following names: DATA<0>, DATA<1>, DATA<2>, and DATA<3>.
To name a wire that contains multiple signals with the same base name, specify the base name followed by a vector expression. The vector expression can be
A list of the individual bit numbers separated by commas and enclosed with angle brackets.
For example, DATA<2,1,0> represents DATA<2>, DATA<1>, and DATA<0>.
A range of numbers containing a lower and upper bound and, optionally, an increment value. The numbers are separated with colons and enclosed with angle brackets.
For example, DATA<1:7:2> represents
baseName<lowerBound:upperBound: [incrValue]>
Use a positive integer for incrValue. If you do not specify an increment value, the editor uses 1.
The ordering of the bits in a bus is important when you are connecting the bus to a pin that has a width greater than 1.
The system evaluates vector expressions in multiple-bit wire names as follows:
The vector expression DATA<0:3:2> names a 2-bit bus containing DATA<0> and DATA<2>.
The vector expression DATA<1:3:2> names a 2-bit bus containing DATA<1> and DATA<3>.
The vector expressions DATA<0:3> and DATA<0:3:1> are equivalent names that generate a 4-bit bus containing DATA<0>, DATA<1>, DATA<2>, and DATA<3>.
If the lower bound is larger than the upper bound, the editor generates the bit numbers in descending order, as follows:
The vector expression DATA<2:0> generates a 3-bit bus that contains DATA<2>, DATA<1>, and DATA<0>.
A multiple-bit wire name can be a bundle, a bus, or a combination of the two. You can improve readability in your designs by shortening multiple-bit wire names.
You can repeat a single signal name, a
group of signal names, or a vector term any number of times in the wire
name by placing a prefix repeat operator <*n> in front of the name, where n is a positive integer that defines the number of times to repeat each bit in the vector term.
Use the prefix repeat operator <*n> to repeat a single-signal name. The following equivalent wire names both name the same four-bit wire:
<*2>A,B,C
A,A,B,C
Use the prefix repeat operator <*n> and parentheses to repeat a group of signal names. The following two wire names are equivalent:
<*2>(A,B),C
A,B,A,B,C
Use combinations of the prefix repeat operator <*n>
and parentheses to nest parenthetical expressions to any required
depth. The editor expands nested expressions from the innermost
expression outward. For example, a name with the expression <*2>(A,<*2>(X,Y)),B expands to A,X,Y,X,Y,A,X,Y,X,Y,B.
A multiple-bit wire name can be a bundle, a bus, or a combination of the two. You can improve readability in your designs by shortening multiple-bit wire names using vector expressions.
A suffix repeat operator is a number, <*n>, after a vector term, where n is a positive integer that defines the number of times to repeat each bit in the vector term.
Use the suffix repeat operator <*n>
to repeat each bit in a group of bit names before expanding the vector
term. For example, the following three names all describe the same
six-bit wire:
A<0:2*2>
A<0*2,1*2,2*2>
A<0,0,1,1,2,2>
Use the suffix repeat operator <*n> and parentheses to repeat the sequence of bit names. In this case, the vector term is expanded before the bits are repeated. The following names all describe the same six-bit wire:
A<(0:2)*2>
A<0:2,0:2>
A<0,1,2,0,1,2>
