SPARC Sun UltraSPARC II处理器

SPARC，全称为“可扩充处理器架构”（Scalable Processor ARChitecture），是RISC微处理器架构之一。它最早于1985年由升阳电脑所设计，也是SPARC国际公司的注册商标之一。这家公司于 1989年成立，其目的是向外界推广SPARC，以及为该架构进行符合性测试。此外该公司为了扩阔SPARC设计的生态系统，SPARC国际也把标准开 放，并授权予多间生产商采用，包括德州仪器、Cypress半导体、富士通等。由于SPARC架构也对外完全开放，因此也出现了完全开放原始码的LEON 处理器，这款处理器以VHDL语言写成，并采用LGPL授权。

SPARC架构原设计给工作站使用，及后应用在升阳、富士通等制造的大型 SMP服务器上。而升阳开发的Solaris操作系统也是为SPARC设计的系统之一，除Solaris外，NeXTSTEP、Linux、 FreeBSD、OpenBSD及NetBSD系统也提供SPARC版本。

现时最新版本的SPARC为第8及第9版，在2005年12月，升阳方面宣布其UltraSPARC T1处理器将采用开放原始码方式。



开源CPU--OpenSparc T1简介 FPGA级别

2006 年3月，Sun宣布开源化其多核心UltraSparc T1 CPU的处理器设计，采用的是GNU通用公共许可证(GNU GPL license)。之前Sun已经公开了"Hypervisor"API规范，允许各公司将Linux、BSD 及其他操作系统移植到UltraSparc T1平台。

Sun是业界首家将复杂的硬件设计使用GNU GPL许可进行发布的公司，而此举也将为UltraSparc T1处理器增加曝光度，并吸引开发人员为该平台开发软硬件解决方案。

该 硬件设计的开源发布包括64-bit UltraSparc T1的Verilog硬件描述语言源代码，验证套装和模拟模型，ISA规范及Solaris 10 OS虚拟镜像。T1处理器的代号为“Niagara”，于去年发布并应用于Sun的T1000/T2000服务器中。 Sun目前推出了4、6、8核心的CPU版本，且每核心最多支持4线程，即总共最多32线程。T1基于Sparc V9架构，每核心集成16KB指令缓存和8KB主数据缓存，整个处理器共享3MB L2缓存。“OpenSparc T1”芯片设计，验证套装，架构和性能模型工具已经发布在网站。Sun还发布了“Cool Tools”，其中包括优化多线程CPU性能的各种程序以及CMT编程及描绘工具。
OpenSparc T1处理器的主要特征包括：
8个Sparc V9处理核心，每核心4线程，共计32线程
每处理核心16KB一级指令缓存，共128KB；

每处理核心8KB一级数据缓存，共64KB；

3MB二级缓存，4-way bank，12向关联，各核心共享；

4个DDR2内存控制器，每通道位宽144bit，总带宽峰值25GB/s；

IEEE754兼容浮点单元(FPU)，各核心共享；

J-Bus输入输出接口，峰值带宽2.56GB/s，128bit多元地址/数据复用总线。



UltraSPARC T1



Sun UltraSPARC T2解析



新 一代的UltraSPARC T2处理器带有8个核心，可以同时处理64个线程。T2的产品代号Niagra 2，不仅将应用在SUN自己的服务器上，还可能放在机顶盒、路由器等设备中。目前处理器由TI负责制造，采用SoC设计，带有2个以太网接口，1个 PCIe ×8接口和4个双通道FBDIMM内存控制器，整个处理器带有5.03亿个晶体管，核心大小342平方毫米，目前共推出1.2GHz与1.4GHz两种频 率，在1.4GHz主频的电压为1.1伏，工作频率上功耗85W。




UltraSPARC T2设计蓝图

65纳米技术更节能

　 　SUN已经成功将90纳米的制作工艺成功转制成65纳米工艺，这样意味着在同样面积的芯片上可以放入更多的模块。此外，T2还使用了其具有革命性的酷线 程(CoolThreads?)芯片多线程技术(CMT)扩展到每线程功耗低于2瓦的UltraSPARC T2处理器。换句话说，拥有这项技术后，SUN的产品功耗将是竞争对手的十分之一或三十分之一。因此我们将看到业界功耗最低、8个内核、64个线程、4倍 的吞吐量及网络和安全的功能性于一身的产品。


芯片特点
处理器     八核心 工作主频在900MHz – 1.4GHz
支持64线程
支持64 FB-DIMMs, 4个内存控制器
内存带宽     60+GB/S
功耗     标准95W或最高123W
其他特点     8个浮点运算单元(FPUs)
双10Gbit以太网接口和PCI-E支持
4MB二级缓存 (8 banks)



每核心1个安全协处理器
核心特点
核心特征     大小：12 mm2
8线程
2条指令管线 + 1个浮点计算 + 1个密码加速单元
8KB 数据缓存+ 16KB 指令缓存
其他应用
其他应用     单插槽的机架或刀片服务器
WiMAX 无线
3G/4G
网络基础构架


性能翻倍，新一代架构有突破

　 　UltraSPARC T2处理器将单一芯片上集成的系统功能提升到空前水平，在性能方面也是T1的两倍。这首先要得益于它较高的吞吐量处理器能力，在 SPECint_rate2006和SPECfp_rate2006的测试中，这两项成绩分别是78.3 est和62.3 est，这主要得益于该处理器的8核和每核8线程的设计特色。在网络连接方面，该处理器支持两个可虚拟化的多线程的每秒10千兆比特的以太网端口，也就是 万兆以太网接口，并具有内建的包分类功能。在安全方面，8个密码加速单元，一共有10个独立的功能，可满足不断增长的安全需求，包括由NSA批准的算法， 在性能上也没有任何损失。

　除此之外，在计算方面8个浮点单元，SUN将CMT的技术优势扩展到了高性能计算领域，适用于各类科学应用， 创立了单芯片 SPECfp_rate2006世界记录和单芯片，有8条通道的输入输出接口可以满足行业标准PCI Express I/O高速应用，如流媒体、数据库读/写，以及数据备份等。4个内存控制器，提供了每秒50千兆字节以上的内存访存速度。

以下表格中公布的是UltraSPARC T2单处理器的性能测试结果：

       SPECint_rate2006      SPECfp_rate2006
 1.4GHz Sun UltraSPARC T2      148％      134％
 4.7GHz IBM POWER 6      115％      125％
 2.66GHz Intel X5355      100％      100％

开源让更多用户受益

　　UltraSparc T2也将和UltraSparc T1一样采用开放原始码授权，到目前为止，OpenSPARC T1源码的下载已经超过5,500次。现在Sun正准备将UltraSPARC T2的源码在上 向OpenSPARC社团发布。并且提供了程序员参考手册、微架构技术规范、OpenSPARC T2β版评估项目等一系列措施，其中程序员参考手册里提供了软件端口、操作系统端口，以及加快OpenSPARC T2项目进展的应用工具。微架构技术规范里提供了对OpenSPARC T2硬件模块特性和功能的详细描述。OpenSPARC T2β版评估项目为一定数量的硬件设计人员和工具开发人员提供早期试用版，让他们开始使用具有片上系统功能性的最新CMT技术。该项目将促进 OpenSPARC T2社团的发展，加快调试过程，以获得性能更佳的OpenSPARC T2的第一个版本，配合具有海量线程特性的Solaris操作系统使高线程处理器UltraSPARC T2的技术优势得到充分发挥，拥有开放的、低成本的虚拟化功能。


官方文章：

Release of OpenSPARC T2 v1.2

http://blogs.sun.com/dv/entry/release_of_opensparc_t2_v1

We are delighted to announce that the new version of OpenSPARC T2 (release 1.2) is now avialable for download from

In the 1.0 release of the OpenSPARC T2, we had to remove two critical IO interface design files - PCI-express and 10G Ethernet - to comply with the legal restrictions. To provide OpenSPARC users alternative means to simulate the entire T2 system-on-chip (SoC) functionality, Sun has developed behavioral models for these two design blocks. These models have similar functionality as the original RTL but are written in the SystemC language. This release, for the first time, allows users to simulate OpenSPARC T2 design with all the IO interfaces of the chip including PCIe and 10G Ethernet. We have also augmented the verification environment, test bench, and test vectors so that users can verify the current design as well as any new variant of it.

Since OpenSPARC T2's PCI-express functionality only supports root-complex configuration, users would need to have access to Denali PureSpec PCI-express model to exercise this model.

Finally, we added one missing piece (64-bit Vector.so library) that would allow OpenSPARC T2 simulation to run under 64-bit Linux operating system which was missing earlier. With this piece in place, T2 simulation can now be run both on 32b as well as 64b Linux platforms on x86 hardware.

 We hope this will encourage work in the areas of IO and SoC design.

Posted on: Jan 29, 2009

Posted by: dv

Category: OpenSPARC

OpenSPARC T2 Version 1.2 Released

The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core.

New Features in Release 1.2

In the 1.0 release of the OpenSPARC T2, we had to remove two critical IO interface design files - PCI-express and 10G Ethernet - to comply with some of the legal restrictions. To provide OpenSPARC users alternative means to simulate the entire T2 system-on-chip (SoC) functionality, Sun has developed behavioral models for these two design blocks. These models have similar functionality as the original RTL but are written in the SystemC language. This release, for the first time, allows users to simulate OpenSPARC T2 design with all the IO interfaces of the chip including PCIe and 10G Ethernet. We have also augmented the verification environment, test bench, and test vectors so that users can verify the current design as well as any new variant of it.

Since OpenSPARC T2's PCI-express functionality only supports root-complex configuration, users would need to have access to Denali PureSpec PCI-express model to exercise this model.

Finally, we added one missing piece (64-bit Vector.so library) that would allow OpenSPARC T2 simulation to run under 64-bit Linux operating system which was missing earlier. With this piece in place, T2 simulation can now be run both on 32b as well as 64b Linux platforms on x86 hardware.

 

and

OpenSPARC T2 Processor Download

OpenSPARC T2 is derived from the UltraSPARC T2 processor. The UltraSPARC T2 processor is industry's first "server on a chip", packaging the most cores and threads of any general-purpose processor available, and integrating all the key functions of a server on a single chip: computing, networking, security, and input/output (I/O), plus tight integration with the Solaris operating system.

By making the source for this design available for a larger community to review and learn from, we expect that ideas around chip multi-threading and multi-core concepts can be explored more freely and openly, and that truly beneficial innovations can be achieved.

Please join the to get up-to-date announcements on this website.

下载Link:

OpenSPARC T2 Processor Download for Chip Design and Verification

OpenSPARC T2 Processor Download for Architecture and Performance Modeling Tools

原文介绍：

OpenSPARC T2 Processor Download

Downloads

Download OpenSPARC T2, a free multi-core, 64-bit multiprocessor and .

• Step 1: Download one or both of the following files and then use bunzip2 command to create OpenSPARCT2.x.x.tar file. e.g. bunzip2 OpenSPARCT2.1.1.tar.bz2
  

  OpenSPARC T2 Chip Design and Verification download
  OpenSPARCT2.1.3.tar.bz2 (bzip2 compression, 278,662,085 bytes)

  OpenSPARC T2 Architecture and Performance Modeling download
  OpenSPARCT2_Arch.1.2.tar.bz2 (bzip2 compression, 373,795,542bytes)

• Step 2:
  Use the following command to extract files from tar file : tar xvf OpenSPARCT2.x.x.tar
  
  
• Step 3:
  For the Chip Design and Verification download, please follow the instructions in the README file in the download to run simulations or synthesis. Also refer to Design/Verification Users Guide document included in the download.
  For the Architecture and Performance Modeling download, please follow the instructions in the README file in the download to setup and run SAM.
  

OpenSPARC T2 Processor Download for Chip Design and Verification

OpenSPARC T2 chip source code is for hardware engineering community with experience in chip design and verification. OpenSPARC T2 source components are covered under multiple open source licenses. The majority of OpenSPARC T2 source code is released under the . Source based on existing open source projects will continue to be available under their current licenses. Binary programs are released under a .

This download area is for hardware design and verification engineers, it includes

• Verilog RTL for OpenSPARC T2 design
• Verification environment for OpenSPARC T2
• Diagnostics tests for OpenSPARC T2
• Scripts and Sun internal tools needed to simulate the design and to do synthesis of the design
• Open source tools needed to simulate the design

System Requirements:

• SPARC CPU based system with Solaris 9 or Solaris 10 Operating System
• C/C++ Compiler, if you don't have it download Sun Studio 12 (it's free too!).

Commercial EDA tools Requirements:

• Verilog Simulator : Synopsys VCS©
• Synthesis : Synopsys Design Compiler©

OpenSPARC T2 Processor Download for Architecture and Performance Modeling Tools

SAM (SPARC Architectural Model) is a full system simulator that is able to boot hypervisor, OBP (Open Boot PROM) and Solaris and run applications. It loads SAS (SPARC Architecture Simulator) as the OpenSPARC T2 simulator. So any modifications made in SAS get automatically reflected in SAM. SAM is useful for software bringup work -- for instance to debug Hypervisor/OBP/Solaris on a modified CPU implementation. SAM is also useful for performance analysis, both to generate traces and to connect with a performance model to perform execution driven simulation. SAM loads device models as dynamically linked libraries, and is useful for device driver development, and device RTL verification.

Legion is a fast instruction accurate simulator which provides a rapid means of developing and testing software functionality in the absence of actual hardware. Legion provides the fastest simulation environment for developing and testing SPARC Software. Firmware and Software developers will be the primary users of Legion simulation environment for the OpenSPARC T2.

OpenSPARC T2 source components are covered under multiple open source licenses. The majority of OpenSPARC T2 source code is released under the . Source based on existing open source projects will continue to be available under their current licenses. Binary programs are released under a .

This download area is for software engineers and architects, it includes;

• SAM - SPARC Architecture Model (including source code)
• Legion - Fast instruction accurate simulator for software developers (including source code)
• SAM/Legion enhancements to copy files to/from simulated disk
• SAS - Instruction accurate SPARC Architecture Simulator (including source code)
• OBP - Open Boot PROM source code
• Hypervisor source code
• Solaris Images for simulation
• RST Trace Tool - RST is a trace format for SPARC instruction-level traces. The RST Tools package consists of the trace format definition, a trace reader/writer library, and a trace viewer program.

System Requirements:

• SPARC CPU based system with Solaris 9 or Solaris 10 Operating System
• C/C++ Compiler, if you don't have it download Sun Studio 12 (it's free too!).

Related Tools

- is a fast SPARC instruction set simulator that is used to perform a variety of analysis functions on SPARC executables.

• Download
• Download