AR5416 ART Table

Atheros based WLAN devices contain an ART block which was stored on the last sector of the flash. ART stands for Atheros Radio Test. It consists of two parts Radio data and board data. Radio data used to tune the output power receiver sensitivity for the RF IC. Mac address, regdomain are recorded in the board data part. You can config the driver by modify this data without changing the madwifi source code. Also some paramters can be overrided by wireless tool commands. So I think Atheros WLAN diver is really well designed.

AR5416EEPROM Header information dumped in the madwifi

=======================Header Information======================
 |  Major Version           14  |  Minor Version           15  |
 |-------------------------------------------------------------|
 |  Checksum           0xD446   |  Length             0x0CB8   |
 |  RegDomain 1        0x0088   |  RegDomain 2        0x1F1F   |
 |  MacAddress: 0x00:03:7F:04:82:28                            |
 |  TX Mask            0x0005   |  RX Mask            0x0007   |
 |  OpFlags: 5GHz 1, 2GHz 1, Disable 5HT40 0, Disable 2HT40 0  |
 |  OpFlags: Disable 5HT20 0, Disable 2HT20 0                  |
 |  Misc: Big Endian 1                                         |
 |  Cal Bin Maj Ver   0 Cal Bin Min Ver   7 Cal Bin Build   6  |
 |  Device Type: Access Point                                  |
 |  Customer Data in hex                                       |
 |= 0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx =|
 |======================5GHz Modal Header======================|
 |  Ant Chain 0     0x0003FFC0  |  Ant Chain 1     0x0001BFC0  |
 |  Ant Chain 2     0x0001BFC0  |
 |  Antenna Common  0x00001120  |  Antenna Gain Chain 0     0  |
 |  Antenna Gain Chain 1     0  |  Antenna Gain Chain 2     0  |
 |  Switch Settling         45  |  TxRxAttenuation Ch 0    46  |
 |  TxRxAttenuation Ch 1    46  |  TxRxAttenuation Ch 2    46  |
 |  RxTxMargin Chain 0      11  |  RxTxMargin Chain 1      11  |
 |  RxTxMargin Chain 2      11  |  adc desired size       226  |
 |  pga desired size       182  |  tx end to xlna on        2  |
 |  xlna gain Chain 0       14  |  xlna gain Chain 1       14  |
 |  xlna gain Chain 2       14  |  tx end to xpa off        0  |
 |  tx frame to xpa on      14  |  thresh62                15  |
 |  noise floor thres 0    202  |  noise floor thres 1    202  |
 |  noise floor thres 2    202  |  Xpd Gain Mask 0xA | Xpd  1  |
 |  IQ Cal I Chain 0         0  |  IQ Cal Q Chain 0         0  |
 |  IQ Cal I Chain 1         0  |  IQ Cal Q Chain 1         0  |
 |  IQ Cal I Chain 2         0  |  IQ Cal Q Chain 2         0  |
 |  pdGain Overlap      3.0 dB  |  Analog Output Bias (ob)  5  |
 |  Analog Driver Bias (db)  5  |  Xpa bias level           0  |
 |  pwr dec 2 chain     0.0 dB  |  pwr dec 3 chain     0.0 dB  |
 |  txFrameToDataStart      14  |  txFrameToPaOn           14  |
 |  ht40PowerIncForPdadc     2  |  bswAtten Chain 0         0  |
 |======================2GHz Modal Header======================|
 |  Ant Chain 0     0x0001BFC0  |  Ant Chain 1     0x0001BFC0  |
 |  Ant Chain 2     0x0001BFC0  |
 |  Antenna Common  0x00001120  |  Antenna Gain Chain 0     0  |
 |  Antenna Gain Chain 1     0  |  Antenna Gain Chain 2     0  |
 |  Switch Settling         45  |  TxRxAttenuation Ch 0    23  |
 |  TxRxAttenuation Ch 1    23  |  TxRxAttenuation Ch 2    23  |
 |  RxTxMargin Chain 0      10  |  RxTxMargin Chain 1      10  |
 |  RxTxMargin Chain 2      10  |  adc desired size       226  |
 |  pga desired size       176  |  tx end to xlna on        2  |
 |  xlna gain Chain 0       13  |  xlna gain Chain 1       13  |
 |  xlna gain Chain 2       13  |  tx end to xpa off        0  |
 |  tx frame to xpa on      14  |  thresh62                28  |
 |  noise floor thres 0    255  |  noise floor thres 1    255  |
 |  noise floor thres 2    255  |  Xpd Gain Mask 0xA | Xpd  1  |
 |  IQ Cal I Chain 0         0  |  IQ Cal Q Chain 0         0  |
 |  IQ Cal I Chain 1         0  |  IQ Cal Q Chain 1         0  |
 |  IQ Cal I Chain 2         0  |  IQ Cal Q Chain 2         0  |
 |  pdGain Overlap      3.0 dB  |  Analog Output Bias (ob)  7  |
 |  Analog Driver Bias (db)  4  |  Xpa bias level           0  |
 |  pwr dec 2 chain     0.0 dB  |  pwr dec 3 chain     0.0 dB  |
 |  txFrameToDataStart      14  |  txFrameToPaOn           14  |
 |  ht40PowerIncForPdadc     2  |  bswAtten Chain 0         0  |
 |=============================================================|

-------------------------------------------------
|offset | length | name                  |
|------------------------------------------------
|0x1000 |    6   | eth0 macaddress        |
-------------------------------------------------
|0x1006 |    6   | eth1 macaddress        |
-------------------------------------------------
|0x1200 |    2   | len of ar5416eeprom      |
-------------------------------------------------
|0x1202 |    2   | checksum for ar5416eeprom    |
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|0x1208 |    2   | regdomain 0  (MKK5_MKKC)     |
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|0x120a |    2   | regdomain ext (HT40 Flag)    |
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