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分类: LINUX

2008-06-27 15:50:25

    下载了u-boot,看了看里面的代码,并加入了一些注释,由于刚开始学arm以及汇编,因此加入了一些对汇编的注释:
    包含如下文件:
    1. board/lowlevel_init.S
    2. cpu/arm920t/start.S

    下面是start.S的内容:

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001    Marius Gr鰃er
 *  Copyright (c) 2002    Alex Z黳ke
 *  Copyright (c) 2002    Gary Jennejohn
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include
#include
#include

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:    b       start_code
    ldr    pc, _undefined_instruction
    ldr    pc, _software_interrupt
    ldr    pc, _prefetch_abort
    ldr    pc, _data_abort
    ldr    pc, _not_used
    ldr    pc, _irq
    ldr    pc, _fiq

_undefined_instruction:    .word undefined_instruction
_software_interrupt:    .word software_interrupt
_prefetch_abort:    .word prefetch_abort
_data_abort:        .word data_abort
_not_used:        .word not_used
_irq:            .word irq
_fiq:            .word fiq

    .balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (called from the ARM reset exception vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

_TEXT_BASE:
    .word    TEXT_BASE

.globl _armboot_start
_armboot_start:
    .word _start

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
    .word __bss_start

.globl _bss_end
_bss_end:
    .word _end

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
    .word    0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
    .word 0x0badc0de
#endif


/*
 * the actual start code
 */

start_code:
    /*
     * set the cpu to SVC32 mode
     */
    mrs    r0,cpsr /*get the cpsr to r0*/
    bic    r0,r0,#0x1f /*bit clear the mode bits to 0 */
    orr    r0,r0,#0xd3 /*set the mode to the svc32 mode, and disable irq and firq at the same time*/
    msr    cpsr,r0 /*set the cpsr*/

    bl coloured_LED_init /*call subroutine, bl is the branch with link instruction, init the led, the coloured_LED_init() is in status_led.h*/
    bl red_LED_on

#if    defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
    /*
     * relocate exception table
     */
    ldr    r0, =_start
    ldr    r1, =0x0
    mov    r2, #16
copyex:
    subs    r2, r2, #1
    ldr    r3, [r0], #4
    str    r3, [r1], #4
    bne    copyex
#endif

#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
    /* turn off the watchdog */

# if defined(CONFIG_S3C2400)
#  define pWTCON        0x15300000
#  define INTMSK        0x14400008    /* Interupt-Controller base addresses */
#  define CLKDIVN    0x14800014    /* clock divisor register */
#else
#  define pWTCON        0x53000000
#  define INTMSK        0x4A000008    /* Interupt-Controller base addresses */
#  define INTSUBMSK    0x4A00001C
#  define CLKDIVN    0x4C000014    /* clock divisor register */
# endif

    ldr     r0, =pWTCON /*here, the ldr is a directive instruction, it will be divided into multiple instructions, which load the address represented by pWTCON to the r0 register*/
    mov     r1, #0x0
    str     r1, [r0] /*store 0 to the watchdog controller*/

    /*
     * mask all IRQs by setting all bits in the INTMR - default
     */
    mov    r1, #0xffffffff /*when moving imediate data into registers, the data should be the result of shifting even number of bits from a 8bit number*/
    ldr    r0, =INTMSK
    str    r1, [r0] /*disable all ints*/
# if defined(CONFIG_S3C2410)
    ldr    r1, =0x3ff
    ldr    r0, =INTSUBMSK
    str    r1, [r0]
# endif

    /* FCLK:HCLK:PCLK = 1:2:4 */
    /* default FCLK is 120 MHz ! */
    ldr    r0, =CLKDIVN /*clock division register*/
    mov    r1, #3
    str    r1, [r0]
#endif    /* CONFIG_S3C2400 || CONFIG_S3C2410 */

    /*
     * we do sys-critical inits only at reboot,
     * not when booting from ram!
     */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl    cpu_init_crit
#endif

#ifdef    CONFIG_AT91RM9200

#ifndef CONFIG_SKIP_RELOCATE_UBOOT
    /* adr put the address of _start into r0, ldr put the content at _TEXT_BASE into r1, that is the
     predetermined value "TEXT_BASE"*/
relocate:                /* relocate U-Boot to RAM        */
    adr    r0, _start        /* r0 <- current position of code   */
    ldr    r1, _TEXT_BASE        /* test if we run from flash or RAM */
    cmp     r0, r1                  /* don't reloc during debug         */
    beq     stack_setup

    ldr    r2, _armboot_start
    ldr    r3, _bss_start
    sub    r2, r3, r2        /* r2 <- size of armboot            */
    add    r2, r0, r2        /* r2 <- source end address         */

copy_loop:
    /* use the group load and store instructions from or to memory
     ldmia and stmia, ! means to adjust the value of the register automatically
     after the transsion*/
    ldmia    r0!, {r3-r10}        /* copy from source address [r0]    */
    stmia    r1!, {r3-r10}        /* copy to   target address [r1]    */
    cmp    r0, r2            /* until source end addreee [r2]    */
    ble    copy_loop
#endif    /* CONFIG_SKIP_RELOCATE_UBOOT */
#endif
    /* Set up the stack                            */
stack_setup:
    ldr    r0, _TEXT_BASE        /* upper 128 KiB: relocated uboot   */
    sub    r0, r0, #CFG_MALLOC_LEN    /* malloc area                      */
    sub    r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
#ifdef CONFIG_USE_IRQ
    sub    r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
    sub    sp, r0, #12        /* leave 3 words for abort-stack    */

clear_bss:
    ldr    r0, _bss_start        /* find start of bss segment        */
    ldr    r1, _bss_end        /* stop here                        */
    mov     r2, #0x00000000        /* clear                            */

clbss_l:str    r2, [r0]        /* clear loop...                    */
    add    r0, r0, #4
    cmp    r0, r1
    ble    clbss_l

    ldr    pc, _start_armboot

_start_armboot:    .word start_armboot


/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
    /*
     * flush v4 I/D caches
     */
    /* mcr and mrc are co-processor instructions, they transfer data from or to the co-processors
     between the registers of the cpu and co-processors*/
    mov    r0, #0

    /* copy 0 to register c7 of co-processor p15 from register r0 from our cpu */
    mcr    p15, 0, r0, c7, c7, 0    /* flush v3/v4 cache, invalidate i-cache and d-cache */

    /* tlbs are page table caches*/
    mcr    p15, 0, r0, c8, c7, 0    /* flush v4 TLB, invalidate TLBs, including i-tlb and d-tlb */

    /*
     * disable MMU stuff and caches
     */
    mrc    p15, 0, r0, c1, c0, 0  /* get the control register's content*/
    bic    r0, r0, #0x00002300    @ clear bits 13, 9:8 (--V- --RS)
    bic    r0, r0, #0x00000087    @ clear bits 7, 2:0 (B--- -CAM)
    orr    r0, r0, #0x00000002    @ set bit 2 (A) Align
    orr    r0, r0, #0x00001000    @ set bit 12 (I) I-Cache
    mcr    p15, 0, r0, c1, c0, 0

    /*
     * before relocating, we have to setup RAM timing
     * because memory timing is board-dependend, you will
     * find a lowlevel_init.S in your board directory.
     */

    /* we are now runing in flash, the ram has not been initialized*/
    /* here, as we are in cpu_init_crit and we are called by start_code , so
     if we call another code section using "bl", we should save the lr register
     which stores the position of the call_site in start_code. we temply copy it
     to ip (R12, it is not PC). when lowlevel_init returns, we restore the R12 to lr
            and call "mov pc, lr" to return the start_code */
    mov    ip, lr
#if    defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)

#else
    bl    lowlevel_init
#endif
    mov    lr, ip
    mov    pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE    72

#define S_OLD_R0    68
#define S_PSR        64
#define S_PC        60
#define S_LR        56
#define S_SP        52

#define S_IP        48
#define S_FP        44
#define S_R10        40
#define S_R9        36
#define S_R8        32
#define S_R7        28
#define S_R6        24
#define S_R5        20
#define S_R4        16
#define S_R3        12
#define S_R2        8
#define S_R1        4
#define S_R0        0

#define MODE_SVC 0x13
#define I_BIT     0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

    .macro    bad_save_user_regs
    sub    sp, sp, #S_FRAME_SIZE
    stmia    sp, {r0 - r12}            @ Calling r0-r12
    ldr    r2, _armboot_start
    sub    r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
    sub    r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
    ldmia    r2, {r2 - r3}            @ get pc, cpsr
    add    r0, sp, #S_FRAME_SIZE        @ restore sp_SVC

    add    r5, sp, #S_SP
    mov    r1, lr
    stmia    r5, {r0 - r3}            @ save sp_SVC, lr_SVC, pc, cpsr
    mov    r0, sp
    .endm

    .macro    irq_save_user_regs
    sub    sp, sp, #S_FRAME_SIZE
    stmia    sp, {r0 - r12}            @ Calling r0-r12
    add     r7, sp, #S_PC
    stmdb   r7, {sp, lr}^                   @ Calling SP, LR
    str     lr, [r7, #0]                    @ Save calling PC
    mrs     r6, spsr
    str     r6, [r7, #4]                    @ Save CPSR
    str     r0, [r7, #8]                    @ Save OLD_R0
    mov    r0, sp
    .endm

    .macro    irq_restore_user_regs
    ldmia    sp, {r0 - lr}^            @ Calling r0 - lr
    mov    r0, r0
    ldr    lr, [sp, #S_PC]            @ Get PC
    add    sp, sp, #S_FRAME_SIZE
    subs    pc, lr, #4            @ return & move spsr_svc into cpsr
    .endm

    .macro get_bad_stack
    ldr    r13, _armboot_start        @ setup our mode stack
    sub    r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
    sub    r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

    str    lr, [r13]            @ save caller lr / spsr
    mrs    lr, spsr
    str     lr, [r13, #4]

    mov    r13, #MODE_SVC            @ prepare SVC-Mode
    @ msr    spsr_c, r13
    msr    spsr, r13
    mov    lr, pc
    movs    pc, lr
    .endm

    .macro get_irq_stack            @ setup IRQ stack
    ldr    sp, IRQ_STACK_START
    .endm

    .macro get_fiq_stack            @ setup FIQ stack
    ldr    sp, FIQ_STACK_START
    .endm

/*
 * exception handlers
 */
    .align  5
undefined_instruction:
    get_bad_stack
    bad_save_user_regs
    bl     do_undefined_instruction

    .align    5
software_interrupt:
    get_bad_stack
    bad_save_user_regs
    bl     do_software_interrupt

    .align    5
prefetch_abort:
    get_bad_stack
    bad_save_user_regs
    bl     do_prefetch_abort

    .align    5
data_abort:
    get_bad_stack
    bad_save_user_regs
    bl     do_data_abort

    .align    5
not_used:
    get_bad_stack
    bad_save_user_regs
    bl     do_not_used

#ifdef CONFIG_USE_IRQ

    .align    5
irq:
    get_irq_stack
    irq_save_user_regs
    bl     do_irq
    irq_restore_user_regs

    .align    5
fiq:
    get_fiq_stack
    /* someone ought to write a more effiction fiq_save_user_regs */
    irq_save_user_regs
    bl     do_fiq
    irq_restore_user_regs

#else

    .align    5
irq:
    get_bad_stack
    bad_save_user_regs
    bl     do_irq

    .align    5
fiq:
    get_bad_stack
    bad_save_user_regs
    bl     do_fiq

#endif


接下来是lowlevel_init.S的内容:

/*
 * Memory Setup stuff - taken from blob memsetup.S
 *
 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
 *
 * Modified for the Samsung SMDK2410 by
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG,
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include
#include


/* some parameters for the board */

/*
 *
 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
 *
 * Copyright (C) 2002 Samsung Electronics SW.LEE 
 *
 */

#define BWSCON    0x48000000

/* BWSCON */
#define DW8             (0x0)
#define DW16             (0x1)
#define DW32             (0x2)
#define WAIT             (0x1<<2)
#define UBLB             (0x1<<3)

#define B1_BWSCON          (DW32)
#define B2_BWSCON          (DW16)
#define B3_BWSCON          (DW16 + WAIT + UBLB)
#define B4_BWSCON          (DW16)
#define B5_BWSCON          (DW16)
#define B6_BWSCON          (DW32)
#define B7_BWSCON          (DW32)

/* BANK0CON */
#define B0_Tacs             0x0    /*  0clk */
#define B0_Tcos             0x0    /*  0clk */
#define B0_Tacc             0x7    /* 14clk */
#define B0_Tcoh             0x0    /*  0clk */
#define B0_Tah             0x0    /*  0clk */
#define B0_Tacp             0x0
#define B0_PMC             0x0    /* normal */

/* BANK1CON */
#define B1_Tacs             0x0    /*  0clk */
#define B1_Tcos             0x0    /*  0clk */
#define B1_Tacc             0x7    /* 14clk */
#define B1_Tcoh             0x0    /*  0clk */
#define B1_Tah             0x0    /*  0clk */
#define B1_Tacp             0x0
#define B1_PMC             0x0

#define B2_Tacs             0x0
#define B2_Tcos             0x0
#define B2_Tacc             0x7
#define B2_Tcoh             0x0
#define B2_Tah             0x0
#define B2_Tacp             0x0
#define B2_PMC             0x0

#define B3_Tacs             0x0    /*  0clk */
#define B3_Tcos             0x3    /*  4clk */
#define B3_Tacc             0x7    /* 14clk */
#define B3_Tcoh             0x1    /*  1clk */
#define B3_Tah             0x0    /*  0clk */
#define B3_Tacp             0x3     /*  6clk */
#define B3_PMC             0x0    /* normal */

#define B4_Tacs             0x0    /*  0clk */
#define B4_Tcos             0x0    /*  0clk */
#define B4_Tacc             0x7    /* 14clk */
#define B4_Tcoh             0x0    /*  0clk */
#define B4_Tah             0x0    /*  0clk */
#define B4_Tacp             0x0
#define B4_PMC             0x0    /* normal */

#define B5_Tacs             0x0    /*  0clk */
#define B5_Tcos             0x0    /*  0clk */
#define B5_Tacc             0x7    /* 14clk */
#define B5_Tcoh             0x0    /*  0clk */
#define B5_Tah             0x0    /*  0clk */
#define B5_Tacp             0x0
#define B5_PMC             0x0    /* normal */

#define B6_MT             0x3    /* SDRAM */
#define B6_Trcd              0x1
#define B6_SCAN             0x1    /* 9bit */

#define B7_MT             0x3    /* SDRAM */
#define B7_Trcd             0x1    /* 3clk */
#define B7_SCAN             0x1    /* 9bit */

/* REFRESH parameter */
#define REFEN             0x1    /* Refresh enable */
#define TREFMD             0x0    /* CBR(CAS before RAS)/Auto refresh */
#define Trp             0x0    /* 2clk */
#define Trc             0x3    /* 7clk */
#define Tchr             0x2    /* 3clk */
#define REFCNT             1113    /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/

_TEXT_BASE:
    .word    TEXT_BASE

.globl lowlevel_init
lowlevel_init:
    /* memory control configuration */
    /* make r0 relative the current location so that it */
    /* reads SMRDATA out of FLASH rather than memory ! */
    ldr     r0, =SMRDATA /* this ldr is a directive, not an arm instruction, it just takes the value of SMRDATA into r0*/
    ldr    r1, _TEXT_BASE /* this ldr is a formal arm instruction, it takes the content at the address _TEXT_BASE into r1*/
    sub    r0, r0, r1
    ldr    r1, =BWSCON    /* Bus Width Status Controller */ /*this is a directive, it just fills r1 with BWSCON, which is the address of bus width status controller*/
    add     r2, r0, #13*4 /*r2 points to the end of the SMRDATA section*/
0:
/*copy SMRDATA contents into BWSCON*/
    ldr     r3, [r0], #4
    str     r3, [r1], #4
    cmp     r2, r0
    bne     0b

    /* everything is fine now */
    mov    pc, lr

    /*as we store some imediate numbers into registers, so the compiler may
     create some literial area to store imediate numnber, in order to locate
     them in a position that we can reach that is (+/-4k from the pc), we manually
     create a literal pool using the directive ".ltorg"*/
    .ltorg
/* the literal pools origin */

SMRDATA:
    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
    .word 0x32
    .word 0x30
    .word 0x30

    从start.S开始,执行start_code处的指令,
    1。依次设置为SVC32 mode,
    2。LED init, 就我目前观察,针对s3c2410/smdk2410的板子,其coloured_LED_init的代码是空的,它是__coloured_LED_init函数的alias(使用了GNUC的__attribute__来设置函数间的alias关系)。
    3。关闭watchdog
    4。关中断,INTMASK和SUBINTMASK
    5。设置fclk/hclk/pclk的比例
    6。调用cpu_init_crit代码段
    7。relocate代码段到TEXT_BASE
    8。stack_setup
    9。clear_bss,对BSS段清零
    10。启动start_armboot。

    上面的6,调用cpu_init_crit代码段完成的工作如下:
    主要是memory controll 的配置。通过向BWSCON写入相应配置数据,具体的配置数据在SMRDATA处存储。
    注意只有在lowlevel_init对存储器配置后,才可能将代码relocate到ram中。

    relocate之后,RAM肯定也早就可用了,为了能让u-boot的stage2能运行,需要设立好stack,因为c语言的程序都是要栈的吗。所以就要setup_stack,其结果是预留出一定长度的栈,并且将stack指针放到sp里面去。

    基于对上述代码的分析,可以推出,启动初期的内存布局:
    从低地址到高地址:
    stack,
    abort_stack(12bytes),
    IRQ stack( 包括irq,fiq的stack)
    bdinfor
    malloc area
    text
    bss

    此外,start.S中还包含了interrupt和exception的处理代码,有待进一步分析。start_armboot的代码也有待进一步分析。
   
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盛装舞步开始2013-10-22 15:40:41

xuwei0317:我一直想知道stage1为什么能在0X00地址执行,终于找到了。不过我对你那段/common/hush.c的那段解释有疑问。按我的理解,“造成的结果就是数据段的地址还是flash里的地址”这句话是不成立的。如果没指定地址,编译后的数据段应该紧跟在在程序段之后。为什么要修改r->literal我不清楚,但我觉得应该不是你说的那种原因。

我也感觉数据段地址不应该是flash的地址

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xuwei03172009-03-18 19:08:16

我一直想知道stage1为什么能在0X00地址执行,终于找到了。不过我对你那段/common/hush.c的那段解释有疑问。按我的理解,“造成的结果就是数据段的地址还是flash里的地址”这句话是不成立的。如果没指定地址,编译后的数据段应该紧跟在在程序段之后。为什么要修改r->literal我不清楚,但我觉得应该不是你说的那种原因。