2440 FCLK, HCLK, and PCLK

FCLK, HCLK, and PCLK
FCLK is used by ARM920T.HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block.
PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI.
he S3C2440A supports selection of Dividing Ratio between FCLK, HLCK and PCLK. This ratio is determined by HDIVN and PDIVN of CLKDIVN control register.

看来HDIVN and PDIVN of CLKDIVN control register是决定HCLK和PCLK的关键，现在再来看看

2440 数据手册258 page

CLKDIVN 0x4C000014  R/W Clock divider control register 0x00000000

——更详细请看258 page了。

那现在看看FCLK到底是由谁来决定呢？

在clock&Power Management的开始处，有讲到FCLK是由晶振通过锁相环（PLL）倍频而来的。在slow模式下没有使用PLL就会使FCLK等于晶振的频率。现在往下看看怎么配置。

The Clock Control Logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK). When PLL is configured to a new frequency value, the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time. The clock control logic is also activated at power-on reset and wakeup from power-down mode.

  FCLK要在PLL输出稳定之后才会有效。

在page244 有

FCLK defination
If SLOW mode
   FCLK = input clock/divider ratio
If Normal mode (P, M & S value)
   FCLK = MPLL clock (Mpll)

page257

SLOW_BIT [4]

0 : FCLK = Mpll (MPLL output)
1: SLOW mode
FCLK = input clock/(2xSLOW_VAL), when SLOW_VAL>0
FCLK = input clock, when SLOW_VAL=0.
Input clock = XTIpll or EXTCLK

page298

CLKSEL0
(Note) [6:4] Select source clock with CLKOUT0 pad
000 = MPLL INPUT Clock(XTAL)
001 = UPLL output
010 = FCLK
011 = HCLK
100 = PCLK
101 = DCLK0
11x = reserved

——看来要想测试FCLK、HCLK、PCLK的真实值，使用这样的配置就可以了。不过普通的示波器测试不了。

在page255 有MPLLCON的设置，输出就是FCLK，但是2440的数据手册并没有明说，导致初学者相当郁闷。

等下我使用应用程序看看我的机器设置的主频到底是多少。

 

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