存储器:
LOCKTIME MPLL,UPLL锁定时间寄存器
MPLLCON
UPLLCON
CLKCON 时钟使能设置
CLKSLOW SlowMode模式设置
CLKDIVN 预分频
先设置MPLL,然后通过CLKDIV分频(FCLK,HCLK,PCLK)
void SetClockDivider(int hdivn, int pdivn)
{
// hdivn,pdivn FCLK:HCLK:PCLK
// 0,0 1:1:1
// 0,1 1:1:2
// 1,0 1:2:2
// 1,1 1:2:4
//如果为SlowMode(寄存器CLKSLOW的SLOW_BIT位),MPLL无效,所以返回没必要继续操作
if(SlowMode)
return;
hdivn &= 1;
pdivn &= 1;
sCLKDIVN = (hdivn<<1)|pdivn;
rCLKDIVN = sCLKDIVN;
if(hdivn)
MMU_SetAsyncBusMode();//参考s3c2410 DataSheet 231、545页
else
MMU_SetFastBusMode();
SetHclkPclk();
}
MMU_SetAsyncBusMode
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
MMU_SetFastBusMode
mrc p15,0,r0,c1,c0,0
bic r0,r0,#R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
//只是计算FCLK,HCLK,PCLK频率,并没有直接操作寄存器,系统频率由SetSysFclk()设置
static void SetHclkPclk()
{
if(sCLKDIVN&2)
SYS_HCLK = SYS_FCLK>>1;
else
SYS_HCLK = SYS_FCLK;
if(sCLKDIVN&1)
SYS_PCLK = SYS_HCLK>>1;
else
SYS_PCLK = SYS_HCLK;
}
U8 SetSysFclk(U32 val)
{
U32 i, freq;
U8 mdiv, pdiv, sdiv;
if(SlowMode)
return FALSE;
// PLL Control Register (MPLLCON and UPLLCON)
// Mpll = (m * Fin) / (p * 2的s次方)
// m = (MDIV + 8), p = (PDIV + 2), s = SDIV
// PLL Value Selection Guide
// 1. Fout = m * Fin / (p*2^s), Fvco = m * Fin / p where : m=MDIV+8, p=PDIV+2, s=SDIV
// 2. Fin/(25*p) < 28.449e6/m < Fin/(10*p)
// 3. 0.7 < 3.373/sqrt(m) < 1.8
// 4. 160e6 £ Fvco £ 400e6
// 5. 20e6 £ Fout £ 300e6 ( The max. Fout of the PLL itself is 300Mhz )
// 6. FCLK ³ 3X-tal or 3EXTCLK
mdiv = (val>>12)&0xff;//mdiv=
pdiv = (val>>4)&0x3f;//pdiv=
sdiv = val&0x3;//sdiv=
//p * 2的s次方
i = (pdiv+2);
while(sdiv--)
i *= 2;
freq = ((mdiv+8)*EXT_XTAL_FREQ)/i;
if(freq>=(3*EXT_XTAL_FREQ)) {
rMPLLCON = val;
SYS_FCLK = freq;
SetHclkPclk();
if(os_timer_run) {
os_timer_rld = SYS_PCLK/(8*4*Timer4Freq)-1;
chg_os_timer = 1;
}
if(bios_timer_run) {
bios_timer_rld = SYS_PCLK/(8*4*BIOS_TIMER_FREQ)-1;
chg_bios_timer = 1;
}
return TRUE;
}
return FALSE;
}
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