内存初始化

一、2440内存初始化
1.2440地址空间
1.1 s3c2440芯片地址线
    总共27根地址线--> Addr[0:26] -->只有访问128M的外设空间
--> 但有8个片选 --> 128MB*8 = 1024MB的内存空间

1.2片选信号
为了扩大外设的访问范围，S3c2440芯片又提供了8个片选信号nGCS0~nGCS7。当某个片选信号nGCSx有效时，则可以通过27根地址线去访问对应这个片选的128MB空间。由于有8个片选，所以2440芯片能访问的外设空间总共为8*128MB=1GB而1G(0x40000000)以上的空间，则安排给了2440内部的寄存器，访问这些内部的寄存器，则是通过32位的处理器内部总线来完成的。

1.3 分析S3c2440芯片外设地址空间

图中可知SRAM总共有8个部分，内存是放在片选6中。所以内存的起始地址是0x3000_0000

1.4存储控制器

存储控制器：用于分解地址--> 行地址，列地址，L-Bank
初始化内存其实就是初始化存储控制器。

2.内存芯片硬件连接
2.1内存芯片连接
①片选信号
②L-Bank选择信号
③行地址
④列地址
4*4*16bit  -->表示单元格数量和数据宽度
因为S3C2440有32条数据线，如果只用16条就太浪费了。把两个32Mb的内存并联到一起，32条地址线同时读取连个芯片。达到了64MB的内存容量。

3.存储控制器寄存器

4.初始化代码

#define mem_contrl 0x48000000
init_sdram:
    ldr r0, =mem_contrl                   将起始地址存入r0
    add r3, r0, #4*13                     将r0加上4*13的长度算出寄存器组的结尾地址
    adrl r1, mem_data                     读取mem_data的地址到r1中

0:
    ldr r2, [r1], #4                      将r1指向的内容存到r2中，并把r1加上4写回r1
    str r2, [r0], #4                      将r2存到r0所指向的内存地址，并把r0加上4写回r0
    cmp r0, r3                            比较r0和r3
    bne 0b                                跳转0如果不等于
    mov pc, lr                            返回init_sdram

mem_data:
    .long 0x22000000
    .long 0x0700
    .long 0x0700
    .long 0x0700
    .long 0x0700
    .long 0x0700
    .long 0x0700
    .long 0x18001
    .long 0x18001
    .long 0x8c04f5
    .long 0xb1
    .long 0x30
    .long 0x30

二、6410内存初始化
1. 地址空间
S3C6410处理器拥32位地址总线，其寻址空间为4GB。其中高2GB为保留区，低2GB区域又可划分为两部分：主存储区和外设区。


1.1 主存储区-划分
Boot镜像区:这个区域的作用正如它的名字所述，是用来启动ARM系统的。但是这个区域并没有固定的存储 介质与之对应。而是通过修改启动选项，把不同的启动介质映射到该区域。比如说选择了IROM 启动方式后，就把IROM映射到该区域。
内部存储区:这个区域对应着内部的内存地址，iROM和SRAM都是分布在这个区间。0x08000000~0x0bffffff对应着内部ROM，但是IROM实际只有32KB，选择从IROM启动的时候，首先运行就是这里面的程序BL0，这部分代码由三星固。0x0c000000~0x0fffffff对应内部SRAM，实际就是8KB的Steppingstone。
静态存储区:这个区域用于访问挂在外部总线上的设备，比如说NOR flash、oneNand等。这个区域被分割为6个bank，每个bank为128MB，数据宽度最大支持16bit，每个bank由片选Xm0CS[0]~Xm0CS[5] 选中。
保留区:
动态存储区:该区域从0x50000000~0x6fffffff，又分为2个区间，分别占256MB，可以片选Xm1CS[0]~Xm1CS[1]来进行着2个区间的选择。我们6410开发板上256MB的DDR内存就安排在这个区域，这也就是为什么6410的内存地址是从0x50000000开始的原因。

2. 6410内存芯片连接
也是用两个内存芯片做一个大内存

3.初始化内存
来自6410手册
5.4.1 DRAM CONTROLLER INITIALIZATION SEQUENCE

1 Program memc_cmd to ‘3’b100’, which makes DRAM Controller enter ‘Config’ state.

2 Write memory timing parameter, chip configuration, and id configuration registers.

3 Wait 200us to allow SDRAM power and clock to stabilize. However, when CPU starts working, power and

clock would already be stabilized.

4 Execute memory initialization sequence.

5 Program memc_cmd to ‘3’b000’, which makes DRAM Controller enter ‘Ready’ state.

6 Check memory status field in memc_stat until memory status becomes ‘2’b01’, which means ‘Ready’.

5.4.3 DDR/MOBILE DDR SDRAM INITIALIZATION SEQUENCE

1 Program mem_cmd in direct_cmd to ‘2’b10’, which makes DRAM Controller issue ‘NOP’ memory command.

2 Program mem_cmd in direct_cmd to ‘2’b00’, which makes DRAM Controller issue ‘Prechargeall’ memory

command.

3 Program mem_cmd in direct_cmd to ‘2’b11’, which makes DRAM Controller issue ‘Autorefresh’ memory

command.

4 Program mem_cmd in direct_cmd to ‘2’b11’, which makes DRAM Controller issue ‘Autorefresh’ memory

command.

5 Program mem_cmd to ‘2’b10’ in direct_cmd, which makes DRAM Controller issue ‘MRS’ memory command

6 Bank address for EMRS must be set.

7 Program mem_cmd to ‘2’b10’ in direct_cmd, which makes DRAM Controller issue ‘MRS’ memory command.

8 Bank address for MRS must be set.

具体配置参考cpu_init.S 内容过长

三、210内存初始化
1.地址空间
0地址用来映射启动方式
其中DRAM1有1G，DRAM0有512M

2. 6410内存芯片连接
210开发板的内存通常采用8片或者4片128M*8bit芯片级联的办法。
3.芯片手册学习
1.2.1.3 DDR2
Initialization sequence for DDR2 memory type:
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to ‘1’.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
15. Wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issue two Auto Refresh commands using the DirectCmd register.
23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.