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移植U-Boot.1.2.0到友善之臂SBC2440V4(补:DM9000网卡移植)
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移植U-Boot.1.2.0到友善之臂SBC2440V4 (补:DM9000网卡移植)
昨天《移植U-Boot.1.2.0到友善之臂SBC2440V4(s3c2440AL)》已经上传。里面介绍的移植是用SC8900网卡,而SBC2440V4是双网卡设计,除了SC8900(10M)外,还有DM9000(10/100M).其实要在U-Boot下使用DM9000也是很容易的事,因为U-Boot的DM9000驱动是可用的(虽然有BUG,但功能可以实现)。
移植参考的资料: (1)WeiBing的博客文章: u-boot 1.1.5 移植成功
在这里感谢 WeiBing的分享。 (2)DM9000的英文数据手册。
在《移植U-Boot.1.2.0到友善之臂SBC2440V4(s3c2440AL)》的基础上,在/include/configs/tekkaman2440.h文件中修改添加对DM9000的支持,屏蔽CS8900: /* * Hardware drivers */ //#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ //#define CS8900_BASE 0x19000300 //#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
#define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x20000300 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+4) #define CONFIG_DM9000_USE_16BIT 在这里#define CONFIG_DM9000_BASE 的定义最为重要。不同的板子只要修改这个参数即可。友善之臂的SBC2440V4上的DM9000在BANK4上所以定义为“0x20000300”。有的板子是在BANK1上,就为“0x08000300”。
这样定义完之后,就可以“make”,然后下载到板上运行。ping和tftp都可以实现。但是有些问题:
(1)网卡的MAC地址与你设置的不一样 (2)会有“could not establish link” 的提示,而且在显示MAC地址后很久后才响应。
这两个问题我认为是U-Boot的DM9000源码的BUG。追踪源码可以知道:这些都是发生在int eth_init(bd_t * bd)初始化时的错误。
修正BUG(修改/drivers/dm9000.c文件)
(1)网卡MAC地址错误的解决方法:
/* Initilize dm9000 board */ int eth_init(bd_t * bd) { ......
/* Set Node address */ /* for (i = 0; i < 6; i++) ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); */ //tekkamanninja char *tmp = getenv ("ethaddr"); char *end;
for (i=0; i<6; i++) { bd->bi_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; if (tmp) tmp = (*end) ? end+1 : end; } //tekkamanninja printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); ......
红色的字符是要做的修改:功能是屏蔽原有获取MAC地址的语句,替换成从U-Boot的参数区读取数据并存到bd->bi_enetaddr[i]中。
(2)“could not establish link” 提示和慢响应的解决方法:
/* Initilize dm9000 board */ int eth_init(bd_t * bd) { ......
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
#if 0 i = 0; while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ udelay(1000); i++; if (i == 10000) { printf("could not establish link\n"); return 0; } printf(" link=%d\n",i); }
/* see what we've got */ lnk = phy_read(17) >> 12; printf("operating at "); switch (lnk) { case 1: printf("10M half duplex "); break; case 2: printf("10M full duplex "); break; case 4: printf("100M half duplex "); break; case 8: printf("100M full duplex "); break; default: printf("unknown: %d ", lnk); break; } printf("mode\n"); #endif return 0; }
红色的字符是要做的修改:功能是屏蔽无用的语句。其实被屏蔽的语句是MII接口用的,放在这显然是错误的,无端的浪费了10秒钟。
至此,U-Boot的2440移植结束了,两张网卡要用哪张随你便。只要重新编译一下就好了。GOOD LUCK!
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回目录 移植U-Boot.1.2.0到友善之臂SBC2440V4(S3C2440AL)
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发表于: 2007-10-15,修改于: 2007-10-29 22:33,已浏览2633次,有评论0条
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网友:
homewood
| 时间:2007-10-30 19:47:18 IP地址:58.68.132.★ |
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出现笔误:(多了)
static inline void NF_Cont(u16 cont)
{
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网友:
本站网友 | 时间:2008-01-22 00:02:02 IP地址:58.60.63.★ |
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你好,首先很感谢你文章的分享,我现在也出现了这样的问题:
U-Boot 1.1.4 (Jan 21 2008 - 01:28:30)
U-Boot code: 33F80000 -> 33F99A50 BSS: -> 33F9DC30
RAM Configuration:
Bank #0: 30000000 64 MB
Flash: 2 MB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
dm9000 not found at 0x18000300 id: 0x00000000
MAC: 00:00:00:00:00:00
could not establish link
SMDK2410 #
找不到网卡,lowlevel_init.s的bank3默认接网卡,我的实验箱也是接bank3的,所以我没修改,按你文章的做法,屏蔽CS8900的宏定义,并添加改以下宏:
在smdk2410.h中添加版主上面所说的宏:
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x18000300
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE+4)
#define CONFIG_DM9000_USE_16BIT
然后在board.c原来用到CS89000的地方相应添加如下内容:
#ifdef CONFIG_DRIVER_DM9000
extern int eth_init(bd_t * bd);
#endif
#ifdef CONFIG_DRIVER_DM9000
eth_init(gd->bd);
#endif
烧去后,就出现找不到DM9000,是不是还有什么地方没修改,请指导,谢谢!!!
Blog作者的回复:
你好,我觉得可能是的你的硬件连接和我不一样。我没看过你的原理图不好讲,你可以将原理图发给我。我再帮你看看。
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网友:
lili1984
| 时间:2008-02-20 14:19:47 IP地址:221.200.197.★ |
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我是楼上的,我的问题还是没解决啊……
这个是我的tekkaman2440.c,完全复制了您的代码啊~
而且我在tekkaman2440.h里的确定义了CFG_NAND_LEGACY宏啊,为什么U-BOOT还是在/u-boot-1.2.0/drivers/nand_legacy/nand_legacy.c中找NF_Read、NF_Write等的定义啊??
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2005
* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <s3c2410.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
#endif
/* ------------------------------------------------------------------------- */
#define FCLK_SPEED 1
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
#define M_MDIV 0xC3
#define M_PDIV 0x4
#define M_SDIV 0x1
#elif FCLK_SPEED==1 /* Fout = 405MHz */
#define M_MDIV 0x7f
#define M_PDIV 0x2
#define M_SDIV 0x1
#endif
#define USB_CLOCK 1
#if USB_CLOCK==0
#define U_M_MDIV 0xA1
#define U_M_PDIV 0x3
#define U_M_SDIV 0x1
#elif USB_CLOCK==1
#define U_M_MDIV 0x38
#define U_M_PDIV 0x2
#define U_M_SDIV 0x2
#endif
static inline void delay (unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);
/* set up the I/O ports */
gpio->GPACON = 0x007FFFFF;
gpio->GPBCON = 0x00055556;
gpio->GPBUP = 0x000007FF;
gpio->GPCCON = 0xAAAAAAAA;
gpio->GPCUP = 0x0000FFFF;
gpio->GPDCON = 0xAAAAAAAA;
gpio->GPDUP = 0x0000FFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x0000FFFF;
gpio->GPFCON = 0x000055AA;
gpio->GPFUP = 0x000000FF;
gpio->GPGCON = 0xFF95FF3A;
gpio->GPGUP = 0x0000FFFF;
gpio->GPHCON = 0x0016FAAA;
gpio->GPHUP = 0x000007FF;
gpio->EXTINT0=0x22222222;
gpio->EXTINT1=0x22222222;
gpio->EXTINT2=0x22222222;
/* arch number of S3C2440-Board */
gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x30000100;
icache_enable();
dcache_enable();
gpio->GPBDAT = 0x180;
return 0;
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
typedef enum {
NFCE_LOW,
NFCE_HIGH
} NFCE_STATE;
static inline void NF_Conf(u16 conf)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFCONF = conf;
}
static inline void NF_Cont(u16 cont)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFCONT = cont;
}
static inline void NF_Cmd(u8 cmd)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFCMD = cmd;
}
static inline void NF_CmdW(u8 cmd)
{
NF_Cmd(cmd);
udelay(1);
}
static inline void NF_Addr(u8 addr)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFADDR = addr;
}
static inline void NF_SetCE(NFCE_STATE s)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
switch (s) {
case NFCE_LOW:
nand->NFCONT &= ~(1<<1);
break;
case NFCE_HIGH:
nand->NFCONT |= (1<<1);
break;
}
}
static inline void NF_WaitRB(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
while (!(nand->NFSTAT & (1<<0)));
}
static inline void NF_Write(u8 data)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFDATA = data;
}
static inline u8 NF_Read(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
return(nand->NFDATA);
}
static inline void NF_Init_ECC(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFCONT |= (1<<4);
}
static inline u32 NF_Read_ECC(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
return(nand->NFECC);
}
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
extern ulong nand_probe(ulong physadr);
static inline void NF_Reset(void)
{
int i;
NF_SetCE(NFCE_LOW);
NF_Cmd(0xFF); /* reset command */
for(i = 0; i < 10; i++); /* tWB = 100ns. */
NF_WaitRB(); /* wait 200~500us; */
NF_SetCE(NFCE_HIGH);
}
static inline void NF_Init(void)
{
#if 0
#define TACLS 0
#define TWRPH0 3
#define TWRPH1 0
#else
#define TACLS 0
#define TWRPH0 4
#define TWRPH1 2
#endif
NF_Conf((TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4));
NF_Cont((1<<6)|(1<<4)|(1<<1)|(1<<0));
/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
/* 1 1 1 1, 1 xxx, r xxx, r xxx */
/* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
NF_Reset();
}
void nand_init(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
NF_Init();
#ifdef DEBUG
printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
#endif
printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
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网友:
lili1984
| 时间:2008-02-23 10:52:23 IP地址:221.200.115.★ |
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我的tekkaman2440.h就是按照您的修改方法改的啊……
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */
#define CONFIG_syhf2440 1 /* on a friendly-arm syhf2440X Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
#define USE_920T_MMU 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
*/
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
#define CS8900_BASE 0x19000300
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
/************************************************************
* RTC
************************************************************/
#define CONFIG_RTC_S3C24X0 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | \
CFG_CMD_CACHE | \
CFG_CMD_NAND | \
CFG_CMD_NET | \
/*CFG_CMD_EEPROM |*/ \
/*CFG_CMD_I2C |*/ \
/*CFG_CMD_USB |*/ \
CFG_CMD_REGINFO | \
CFG_CMD_DATE | \
CFG_CMD_PING | \
CFG_CMD_DHCP | \
CFG_CMD_ENV | \
CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.69
#define CONFIG_SERVERIP 192.168.0.1
/*#define CONFIG_BOOTFILE "elinos-lart" */
#define CONFIG_BOOTCOMMAND "dhcp; bootm"
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "[ syhf2440 ]# " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x30008000 /* default load address */
/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define CFG_HZ 1562500
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CFG_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
#endif
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_NAND 1
#define CFG_ENV_OFFSET 0X20000
//#define ENV_IS_EMBEDDED 1
#define CFG_NAND_LEGACY
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* NAND flash settings
*/
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#define CFG_NAND_BASE 0x4E000000
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define NAND_SECTOR_SIZE SECTORSIZE
#define NAND_BLOCK_MASK 511
#define ADDR_COLUMN 1
#define ADDR_PAGE 3
#define ADDR_COLUMN_PAGE 4
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB()
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
#define WRITE_NAND_ADDRESS(d, adr) {rNFADDR = d;}
#define WRITE_NAND(d, adr) {rNFDATA = d;}
#define READ_NAND(adr) (rNFDATA)
#define NAND_WAIT_READY(nand) {while(!(rNFSTAT&(1<<0)));}
#define NAND_DISABLE_CE(nand) {rNFCONT |= (1<<1);}
#define NAND_ENABLE_CE(nand) {rNFCONT &= ~(1<<1);}
#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
#define WRITE_NAND(d, adr) NF_Write(d)
#define READ_NAND(adr) NF_Read()
/* the following functions are NOP's because S3C24X0 handles this in hardware */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#ifdef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
#else
#define CONFIG_AUTO_COMPLETE
#endif
/*
* Nandflash Boot
*/
#define CONFIG_S3C2440_NAND_BOOT 1
#define STACK_BASE 0x33f00000
#define STACK_SIZE 0x8000
//#define UBOOT_RAM_BASE 0x33f80000
/* NAND Flash Controller */
#define NAND_CTL_BASE 0x4E000000
#define bINT_CTL(Nb) __REG(INT_CTL_BASE + (Nb))
/* Offset */
#define oNFCONF 0x00
#define oNFCONT 0x04
#define oNFCMD 0x08
#define oNFADDR 0x0c
#define oNFDATA 0x10
#define oNFSTAT 0x20
#define oNFECC 0x2c
/* GPIO */
#define GPIO_CTL_BASE 0x56000000
#define oGPIO_B 0x10
#define oGPIO_CON 0x0 /* R/W, Configures the pins of the port */
#define oGPIO_DAT 0x4 /* R/W, Data register for port */
#define oGPIO_UP 0x8 /* R/W, Pull-up disable register */
#define rNFCONF (*(volatile unsigned int *)0x4e000000)
#define rNFCONT (*(volatile unsigned int *)0x4e000004)
#define rNFCMD (*(volatile unsigned char *)0x4e000008)
#define rNFADDR (*(volatile unsigned char *)0x4e00000c)
#define rNFDATA (*(volatile unsigned char *)0x4e000010)
#define rNFSTAT (*(volatile unsigned int *)0x4e000020)
#define rNFECC (*(volatile unsigned int *)0x4e00002c)
#endif /* __CONFIG_H */
Blog作者的回复:
兄弟啊!
你的:
define NAND_WAIT_READY(nand) NF_WaitRB()
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
#define WRITE_NAND_ADDRESS(d, adr) {rNFADDR = d;}
#define WRITE_NAND(d, adr) {rNFDATA = d;}
#define READ_NAND(adr) (rNFDATA)
#define NAND_WAIT_READY(nand) {while(!(rNFSTAT&(1<<0)));}
#define NAND_DISABLE_CE(nand) {rNFCONT |= (1<<1);}
#define NAND_ENABLE_CE(nand) {rNFCONT &= ~(1<<1);}
#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
#define WRITE_NAND(d, adr) NF_Write(d)
#define READ_NAND(adr) NF_Read()
和我的
#define WRITE_NAND_COMMAND(d, adr) {rNFCMD = d;}
#define WRITE_NAND_ADDRESS(d, adr) {rNFADDR = d;}
#define WRITE_NAND(d, adr) {rNFDATA = d;}
#define READ_NAND(adr) (rNFDATA)
#define NAND_WAIT_READY(nand) {while(!(rNFSTAT&(1<<0)));}
#define NAND_DISABLE_CE(nand) {rNFCONT |= (1<<1);}
#define NAND_ENABLE_CE(nand) {rNFCONT &= ~(1<<1);}
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
可是差很多啊!!!!!!!
你这样不但重复定义,而且第二次定义中有的还是错的!当然通不过!!
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网友:
本站网友 | 时间:2008-03-31 16:01:42 IP地址:221.232.171.★ |
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楼主你好。不知道你的DM9000在2.6内核中移植成功了没有。
我在ping时一直说network is unreachable 。然后用ifconfig配置eth0也会报错。如果可以的话,能不能把内核的dm9000.c这个文件发给我。
chensi_04@126.com
先谢过了
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网友:
本站网友 | 时间:2008-04-08 20:15:26 IP地址:221.208.253.★ |
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是否能把你的2440的VIVI的源码给我发一份 coolboyppk1999@163.com
万分感谢
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网友:
tgvlcw
| 时间:2008-05-22 17:21:41 IP地址:218.28.87.★ |
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先谢谢楼主提供的代码,我现在的UBOOT可以用了~!tftp可以下载,但是不能保存环境变更和数据到nand flash当中!用saveenv后,复位后无效!不知道问题出在哪了!请楼主指点一下!
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网友:
本站网友 | 时间:2008-06-04 18:27:45 IP地址:121.28.194.★ |
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版主,你好,看了你的“移植U-Boot.1.2.0到友善之臂SBC2440V4(S3C2440AL)”这篇大作后很受启发,回去自己移植uboot时确有两点迷惑,不知如何解决,特来向您请教:
1、 您提到#define CONFIG_DM9000_BASE 的定义最为重要。不同的板子只要修改这个参数即可。友善之臂的SBC2440V4上的DM9000在BANK4上所以定义为0x20000300”。有的板子是在BANK1上,就为“0x08000300”。-----请问判断所谓的BANKx,是用什么判断恩,是DM9000的那根信号线与2440的那根信号相连接而定呢?翻遍了资料就是搞不明白,特请详细说明、给予点拨。
2、 我移植的uboot中#define CONFIG_DM9000_BASE为“010000300”参考别人。启动信息为:
In: serial
Out: serial
Err: serial
Found DM9000 ID:90000a46 at address 10000300, ethaddr = 20:04:12:01:00:01!
DM9000 work in 16 bus width
Not link of ethernet /////提示网络没有连接
Hit any key to stop autoboot: 0
执行reset命令后,启动信息为:
In: serial
Out: serial
Err: serial
Found DM9000 ID:90000a46 at address 10000300, ethaddr = 20:04:12:01:00:01!
DM9000 work in 16 bus width
Link on ethernet at:100 Mbps //////提示网络连接成功,而且网速还是100Mbps呢
Hit any key to stop autoboot: 0
网卡LED点亮,主机ping不到板子,板子ping主机及其自己时信息为:
SMDK2440 # ping 192.168.1.120 /////主机IP
ping failed; host 192.168.1.120 is not alive
SMDK2440 # ping 192.168.1.125 /////板子IP
ping failed; host 192.168.1.125 is not alive
主机tftp服务已经开启,用TFTP命令时,显示信息为:
SMDK2440 # tftp 0x32000000 vmlinux
errorTFTP from server 192.168.1.120; our IP address is 192.168.1.125
Filename 'vmlinux'.
Load address: 0x32000000
Loading: T T T T T T T T T T
Retry count exceeded; starting again
这个问题已经折磨我好几周了,百思不知其解,特望版主能给予点拨,帮助分析下可能出现问题的地方,敬待您的佳音,跪谢!!!
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网友:
本站网友 | 时间:2008-06-13 20:49:39 IP地址:121.28.194.★ |
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版主你好,我按您的大作一步步修改下来了,结果网卡就是不通,具体信息如下,敬请指教;:
U-Boot 1.1.3 (Jun 13 2008 - 09:39:22)
U-Boot code: 33F80000 -> 33FA7958 BSS: -> 33FEA100
RAM Configuration:
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